c39e422eed
self-consistent, there is no need in anything but compiler barrier in the implementation of atomic_thread_fence_*() on ARMv5. Split implementation of fences for ARMv4/5 and ARMv6; the former use compiler barriers, the later also perform hardware barriers. An issue which is fixed by the change is the faults from the CP15 coprocessor accesses in the user mode. This was uncovered by the pthread_once() changes in r287556. Reported by: Mattia Rossi <mattia.rossi.mailinglists@gmail.com> Discussed with: alc, cognet, jhb Sponsored by: The FreeBSD Foundation MFC after: 1 week
114 lines
3.7 KiB
C
114 lines
3.7 KiB
C
/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
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/*-
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* Copyright (C) 2003-2004 Olivier Houchard
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#include <sys/types.h>
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#include <machine/armreg.h>
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#include <machine/acle-compat.h>
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#ifndef _KERNEL
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#include <machine/sysarch.h>
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#else
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#include <machine/cpuconf.h>
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#endif
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#if __ARM_ARCH >= 6
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#include <machine/atomic-v6.h>
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#else /* < armv6 */
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#include <machine/atomic-v4.h>
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#endif /* Arch >= v6 */
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static __inline int
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atomic_load_32(volatile uint32_t *v)
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{
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return (*v);
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}
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static __inline void
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atomic_store_32(volatile uint32_t *dst, uint32_t src)
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{
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*dst = src;
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}
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static __inline int
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atomic_load_long(volatile u_long *v)
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{
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return (*v);
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}
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static __inline void
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atomic_store_long(volatile u_long *dst, u_long src)
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{
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*dst = src;
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}
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#define atomic_clear_ptr atomic_clear_32
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#define atomic_set_ptr atomic_set_32
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#define atomic_cmpset_ptr atomic_cmpset_32
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#define atomic_cmpset_rel_ptr atomic_cmpset_rel_32
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#define atomic_cmpset_acq_ptr atomic_cmpset_acq_32
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#define atomic_store_ptr atomic_store_32
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#define atomic_store_rel_ptr atomic_store_rel_32
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#define atomic_add_int atomic_add_32
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#define atomic_add_acq_int atomic_add_acq_32
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#define atomic_add_rel_int atomic_add_rel_32
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#define atomic_subtract_int atomic_subtract_32
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#define atomic_subtract_acq_int atomic_subtract_acq_32
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#define atomic_subtract_rel_int atomic_subtract_rel_32
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#define atomic_clear_int atomic_clear_32
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#define atomic_clear_acq_int atomic_clear_acq_32
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#define atomic_clear_rel_int atomic_clear_rel_32
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#define atomic_set_int atomic_set_32
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#define atomic_set_acq_int atomic_set_acq_32
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#define atomic_set_rel_int atomic_set_rel_32
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#define atomic_cmpset_int atomic_cmpset_32
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#define atomic_cmpset_acq_int atomic_cmpset_acq_32
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#define atomic_cmpset_rel_int atomic_cmpset_rel_32
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#define atomic_fetchadd_int atomic_fetchadd_32
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#define atomic_readandclear_int atomic_readandclear_32
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#define atomic_load_acq_int atomic_load_acq_32
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#define atomic_store_rel_int atomic_store_rel_32
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#endif /* _MACHINE_ATOMIC_H_ */
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