d1d3233ebd
The following systems are affected: - MPC8555CDS - MPC8572DS This overhaul covers the following major changes: - All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values). - This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI. - Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data. Note that world for these platforms has to be built WITH_FDT. Reviewed by: imp Sponsored by: The FreeBSD Foundation
367 lines
9.0 KiB
C
367 lines
9.0 KiB
C
/*-
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* Copyright (c) 2010 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ktr.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <dev/fdt/fdt_common.h>
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#include <machine/fdt.h>
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#include "ofw_bus_if.h"
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#define DEBUG
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#undef DEBUG
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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#define FDT_RANGES_CELLS ((3 + 3 + 2) * 2)
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static void
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fdt_pci_range_dump(struct fdt_pci_range *range)
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{
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#ifdef DEBUG
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printf("\n");
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printf(" base_pci = 0x%08lx\n", range->base_pci);
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printf(" base_par = 0x%08lx\n", range->base_parent);
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printf(" len = 0x%08lx\n", range->len);
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#endif
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}
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int
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fdt_pci_ranges_decode(phandle_t node, struct fdt_pci_range *io_space,
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struct fdt_pci_range *mem_space)
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{
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pcell_t ranges[FDT_RANGES_CELLS];
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struct fdt_pci_range *pci_space;
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pcell_t addr_cells, size_cells, par_addr_cells;
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pcell_t *rangesptr;
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pcell_t cell0, cell1, cell2;
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int tuple_size, tuples, i, rv, offset_cells, len;
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/*
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* Retrieve 'ranges' property.
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*/
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if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
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return (EINVAL);
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if (addr_cells != 3 || size_cells != 2)
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return (ERANGE);
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par_addr_cells = fdt_parent_addr_cells(node);
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if (par_addr_cells > 3)
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return (ERANGE);
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len = OF_getproplen(node, "ranges");
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if (len > sizeof(ranges))
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return (ENOMEM);
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if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
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return (EINVAL);
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tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
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size_cells);
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tuples = len / tuple_size;
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rangesptr = &ranges[0];
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offset_cells = 0;
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for (i = 0; i < tuples; i++) {
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cell0 = fdt_data_get((void *)rangesptr, 1);
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rangesptr++;
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cell1 = fdt_data_get((void *)rangesptr, 1);
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rangesptr++;
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cell2 = fdt_data_get((void *)rangesptr, 1);
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rangesptr++;
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if (cell0 & 0x02000000) {
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pci_space = mem_space;
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} else if (cell0 & 0x01000000) {
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pci_space = io_space;
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} else {
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rv = ERANGE;
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goto out;
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}
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if (par_addr_cells == 3) {
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/*
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* This is a PCI subnode 'ranges'. Skip cell0 and
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* cell1 of this entry and only use cell2.
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*/
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offset_cells = 2;
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rangesptr += offset_cells;
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}
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if (fdt_data_verify((void *)rangesptr, par_addr_cells -
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offset_cells)) {
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rv = ERANGE;
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goto out;
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}
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pci_space->base_parent = fdt_data_get((void *)rangesptr,
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par_addr_cells - offset_cells);
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rangesptr += par_addr_cells - offset_cells;
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if (fdt_data_verify((void *)rangesptr, size_cells)) {
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rv = ERANGE;
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goto out;
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}
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pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
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rangesptr += size_cells;
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pci_space->base_pci = cell2;
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}
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rv = 0;
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out:
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return (rv);
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}
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int
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fdt_pci_ranges(phandle_t node, struct fdt_pci_range *io_space,
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struct fdt_pci_range *mem_space)
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{
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struct fdt_pci_range par_io_space, par_mem_space;
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u_long base;
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int err;
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debugf("Processing parent PCI node: %x\n", node);
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if ((err = fdt_pci_ranges_decode(OF_parent(node), &par_io_space,
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&par_mem_space)) != 0) {
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debugf("could not decode parent PCI node 'ranges'\n");
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return (err);
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}
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debugf("Processing PCI sub node: %x\n", node);
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if ((err = fdt_pci_ranges_decode(node, io_space, mem_space)) != 0) {
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debugf("could not decode PCI subnode 'ranges'\n");
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return (err);
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}
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base = io_space->base_parent & 0x000fffff;
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base += par_io_space.base_parent;
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io_space->base_parent = base;
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base = mem_space->base_parent & 0x000fffff;
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base += par_mem_space.base_parent;
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mem_space->base_parent = base;
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debugf("Post fixup dump:\n");
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fdt_pci_range_dump(io_space);
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fdt_pci_range_dump(mem_space);
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return (0);
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}
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static int
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fdt_addr_cells(phandle_t node, int *addr_cells)
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{
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pcell_t cell;
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int cell_size;
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cell_size = sizeof(cell);
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if (OF_getprop(node, "#address-cells", &cell, cell_size) < cell_size)
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return (EINVAL);
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*addr_cells = fdt32_to_cpu((int)cell);
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if (*addr_cells > 3)
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return (ERANGE);
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return (0);
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}
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static int
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fdt_interrupt_cells(phandle_t node)
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{
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pcell_t intr_cells;
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if (OF_getprop(node, "#interrupt-cells", &intr_cells,
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sizeof(intr_cells)) <= 0) {
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debugf("no intr-cells defined, defaulting to 1\n");
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intr_cells = 1;
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}
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intr_cells = fdt32_to_cpu(intr_cells);
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return ((int)intr_cells);
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}
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int
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fdt_pci_intr_info(phandle_t node, struct fdt_pci_intr *intr_info)
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{
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void *map, *mask;
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phandle_t pci_par;
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int intr_cells, addr_cells;
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int len;
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addr_cells = fdt_parent_addr_cells(node);
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pci_par = OF_parent(node);
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intr_cells = fdt_interrupt_cells(pci_par);
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/*
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* Retrieve the interrupt map and mask properties.
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*/
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len = OF_getprop_alloc(pci_par, "interrupt-map-mask", 1, &mask);
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if (len / sizeof(pcell_t) != (addr_cells + intr_cells)) {
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debugf("bad mask len = %d\n", len);
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goto err;
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}
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len = OF_getprop_alloc(pci_par, "interrupt-map", 1, &map);
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if (len <= 0) {
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debugf("bad map len = %d\n", len);
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goto err;
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}
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intr_info->map_len = len;
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intr_info->map = map;
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intr_info->mask = mask;
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intr_info->addr_cells = addr_cells;
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intr_info->intr_cells = intr_cells;
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return (0);
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err:
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free(mask, M_OFWPROP);
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return (ENXIO);
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}
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int
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fdt_pci_route_intr(int bus, int slot, int func, int pin,
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struct fdt_pci_intr *intr_info, int *interrupt)
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{
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pcell_t child_spec[4], masked[4];
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ihandle_t iph;
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pcell_t intr_par;
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pcell_t *map_ptr;
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uint32_t addr;
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int i, j, map_len;
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int par_intr_cells, par_addr_cells, child_spec_cells, row_cells;
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int par_idx, spec_idx, err, trig, pol;
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child_spec_cells = intr_info->addr_cells + intr_info->intr_cells;
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if (child_spec_cells > sizeof(child_spec) / sizeof(pcell_t))
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return (ENOMEM);
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addr = (bus << 16) | (slot << 11) | (func << 8);
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child_spec[0] = addr;
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child_spec[1] = 0;
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child_spec[2] = 0;
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child_spec[3] = pin;
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map_len = intr_info->map_len;
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map_ptr = intr_info->map;
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par_idx = child_spec_cells;
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i = 0;
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while (i < map_len) {
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iph = fdt32_to_cpu(map_ptr[par_idx]);
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intr_par = OF_instance_to_package(iph);
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err = fdt_addr_cells(intr_par, &par_addr_cells);
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if (err != 0) {
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debugf("could not retrieve intr parent #addr-cells\n");
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return (err);
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}
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par_intr_cells = fdt_interrupt_cells(intr_par);
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row_cells = child_spec_cells + 1 + par_addr_cells +
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par_intr_cells;
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/*
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* Apply mask and look up the entry in interrupt map.
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*/
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for (j = 0; j < child_spec_cells; j++) {
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masked[j] = child_spec[j] &
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fdt32_to_cpu(intr_info->mask[j]);
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if (masked[j] != fdt32_to_cpu(map_ptr[j]))
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goto next;
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}
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/*
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* Decode interrupt of the parent intr controller.
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*/
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spec_idx = child_spec_cells + 1 + par_addr_cells;
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err = fdt_intr_decode(intr_par, &map_ptr[spec_idx],
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interrupt, &trig, &pol);
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if (err != 0) {
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debugf("could not decode interrupt\n");
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return (err);
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}
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debugf("decoded intr = %d, trig = %d, pol = %d\n", *interrupt,
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trig, pol);
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#if defined(__powerpc__)
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powerpc_config_intr(INTR_VEC(intr_par, *interrupt), trig, pol);
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#endif
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return (0);
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next:
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map_ptr += row_cells;
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i += (row_cells * sizeof(pcell_t));
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}
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return (ENXIO);
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}
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#if defined(__arm__)
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int
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fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, vm_offset_t io_va,
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vm_offset_t mem_va)
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{
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struct fdt_pci_range io_space, mem_space;
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int error;
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if ((error = fdt_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
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return (error);
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devmap->pd_va = io_va;
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devmap->pd_pa = io_space.base_parent;
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devmap->pd_size = io_space.len;
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devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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devmap->pd_cache = PTE_NOCACHE;
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devmap++;
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devmap->pd_va = mem_va;
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devmap->pd_pa = mem_space.base_parent;
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devmap->pd_size = mem_space.len;
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devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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devmap->pd_cache = PTE_NOCACHE;
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return (0);
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}
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#endif
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