freebsd-dev/sys/dev/usb/controller
Michal Meloun c520cb4f50 ehci_interrupt is MPSAFE code. Most drivers in tree calls bus_setup_intr
with MPSAFE, some are not. Fix those.

Submitted by: Howard Su <howard0su@gmail.com>
Differential Revision: https://reviews.freebsd.org/D5755
2016-04-05 12:13:53 +00:00
..
at91dci_atmelarm.c
at91dci_fdt.c
at91dci.c
at91dci.h
atmegadci_atmelarm.c
atmegadci.c
atmegadci.h
avr32dci.c
avr32dci.h
dwc_otg_fdt.c
dwc_otg_fdt.h
dwc_otg_hisi.c
dwc_otg.c Fix for directly connected FULL or LOW speed USB devices. 2016-01-05 09:18:43 +00:00
dwc_otg.h Avoid using the bounce buffer when the source or destination buffer is 2015-11-08 09:37:26 +00:00
dwc_otgreg.h
ehci_fsl.c ehci_interrupt is MPSAFE code. Most drivers in tree calls bus_setup_intr 2016-04-05 12:13:53 +00:00
ehci_imx.c ehci_interrupt is MPSAFE code. Most drivers in tree calls bus_setup_intr 2016-04-05 12:13:53 +00:00
ehci_ixp4xx.c EHCI: Make core reset and port speed reading more generic. 2016-01-28 14:11:59 +00:00
ehci_mv.c EHCI: Make core reset and port speed reading more generic. 2016-01-28 14:11:59 +00:00
ehci_pci.c Add some device IDs found on AMD FCH shipsets. 2016-03-29 12:50:42 +00:00
ehci.c EHCI: Make core reset and port speed reading more generic. 2016-01-28 14:11:59 +00:00
ehci.h EHCI: Make core reset and port speed reading more generic. 2016-01-28 14:11:59 +00:00
ehcireg.h EHCI: Correct address of EHCI_USBMODE_LPM register is 0xC8, not 0xA8. 2016-01-30 08:27:09 +00:00
musb_otg_atmelarm.c
musb_otg.c
musb_otg.h
ohci_pci.c Add some device IDs found on AMD FCH shipsets. 2016-03-29 12:50:42 +00:00
ohci_s3c24x0.c
ohci.c
ohci.h
ohcireg.h
saf1761_otg_boot.c
saf1761_otg_fdt.c
saf1761_otg_reg.h
saf1761_otg.c
saf1761_otg.h
uhci_pci.c Add more UHCI PCI IDs. 2016-03-24 09:35:29 +00:00
uhci.c
uhci.h Fix compile warning about shifting signed negative constant. 2015-11-23 12:55:37 +00:00
uhcireg.h
usb_controller.c
uss820dci_atmelarm.c
uss820dci.c
uss820dci.h
xhci_mv.c Add xhci_mv.c 2016-03-14 07:24:08 +00:00
xhci_pci.c Add some device IDs found on AMD FCH shipsets. 2016-03-29 12:50:42 +00:00
xhci.c Configure the correct bMaxPacketSize for control endpoints before 2016-02-23 18:17:01 +00:00
xhci.h Configure the correct bMaxPacketSize for control endpoints before 2016-02-23 18:17:01 +00:00
xhcireg.h