c5e423dd2e
the proper ICWx initialization sequence. It assumes, probably correctly, that the boot firmware has done the 8259 initialization. Since grub-bhyve does not initialize the 8259 this write to the mask register takes a code path in which 'error' remains uninitialized (ready=0,icw_num=0). Fix this by initializing 'error' at the start of the function.
735 lines
16 KiB
C
735 lines
16 KiB
C
/*-
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* Copyright (c) 2014 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/queue.h>
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#include <sys/cpuset.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/systm.h>
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#include <x86/apicreg.h>
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#include <dev/ic/i8259.h>
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#include <machine/vmm.h>
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#include "vmm_ktr.h"
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#include "vmm_lapic.h"
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#include "vioapic.h"
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#include "vatpic.h"
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static MALLOC_DEFINE(M_VATPIC, "atpic", "bhyve virtual atpic (8259)");
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#define VATPIC_LOCK(vatpic) mtx_lock_spin(&((vatpic)->mtx))
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#define VATPIC_UNLOCK(vatpic) mtx_unlock_spin(&((vatpic)->mtx))
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#define VATPIC_LOCKED(vatpic) mtx_owned(&((vatpic)->mtx))
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enum irqstate {
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IRQSTATE_ASSERT,
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IRQSTATE_DEASSERT,
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IRQSTATE_PULSE
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};
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struct atpic {
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bool ready;
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int icw_num;
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int rd_cmd_reg;
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bool aeoi;
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bool poll;
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bool rotate;
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bool sfn; /* special fully-nested mode */
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int irq_base;
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uint8_t request; /* Interrupt Request Register (IIR) */
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uint8_t service; /* Interrupt Service (ISR) */
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uint8_t mask; /* Interrupt Mask Register (IMR) */
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int acnt[8]; /* sum of pin asserts and deasserts */
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int priority; /* current pin priority */
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bool intr_raised;
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};
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struct vatpic {
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struct vm *vm;
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struct mtx mtx;
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struct atpic atpic[2];
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uint8_t elc[2];
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};
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#define VATPIC_CTR0(vatpic, fmt) \
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VM_CTR0((vatpic)->vm, fmt)
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#define VATPIC_CTR1(vatpic, fmt, a1) \
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VM_CTR1((vatpic)->vm, fmt, a1)
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#define VATPIC_CTR2(vatpic, fmt, a1, a2) \
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VM_CTR2((vatpic)->vm, fmt, a1, a2)
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#define VATPIC_CTR3(vatpic, fmt, a1, a2, a3) \
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VM_CTR3((vatpic)->vm, fmt, a1, a2, a3)
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#define VATPIC_CTR4(vatpic, fmt, a1, a2, a3, a4) \
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VM_CTR4((vatpic)->vm, fmt, a1, a2, a3, a4)
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static void vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate);
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static __inline int
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vatpic_get_highest_isrpin(struct atpic *atpic)
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{
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int bit, pin;
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int i;
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for (i = 0; i <= 7; i++) {
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pin = ((i + 7 - atpic->priority) & 0x7);
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bit = (1 << pin);
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if (atpic->service & bit)
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return (pin);
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}
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return (-1);
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}
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static __inline int
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vatpic_get_highest_irrpin(struct atpic *atpic)
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{
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int serviced;
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int bit, pin;
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int i, j;
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/*
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* In 'Special Fully-Nested Mode' when an interrupt request from
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* a slave is in service, the slave is not locked out from the
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* master's priority logic.
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*/
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serviced = atpic->service;
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if (atpic->sfn)
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serviced &= ~(1 << 2);
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for (i = 0; i <= 7; i++) {
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pin = ((i + 7 - atpic->priority) & 0x7);
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bit = (1 << pin);
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if (serviced & bit)
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break;
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}
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for (j = 0; j < i; j++) {
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pin = ((j + 7 - atpic->priority) & 0x7);
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bit = (1 << pin);
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if (atpic->request & bit && (~atpic->mask & bit))
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return (pin);
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}
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return (-1);
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}
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static void
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vatpic_notify_intr(struct vatpic *vatpic)
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{
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struct atpic *atpic;
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int pin;
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KASSERT(VATPIC_LOCKED(vatpic), ("vatpic_notify_intr not locked"));
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/*
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* First check the slave.
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*/
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atpic = &vatpic->atpic[1];
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if (!atpic->intr_raised &&
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(pin = vatpic_get_highest_irrpin(atpic)) != -1) {
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VATPIC_CTR4(vatpic, "atpic slave notify pin = %d "
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"(imr 0x%x irr 0x%x isr 0x%x)", pin,
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atpic->mask, atpic->request, atpic->service);
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/*
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* Cascade the request from the slave to the master.
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*/
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atpic->intr_raised = true;
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vatpic_set_pinstate(vatpic, 2, true);
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vatpic_set_pinstate(vatpic, 2, false);
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} else {
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VATPIC_CTR3(vatpic, "atpic slave no eligible interrupts "
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"(imr 0x%x irr 0x%x isr 0x%x)",
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atpic->mask, atpic->request, atpic->service);
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}
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/*
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* Then check the master.
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*/
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atpic = &vatpic->atpic[0];
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if (!atpic->intr_raised &&
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(pin = vatpic_get_highest_irrpin(atpic)) != -1) {
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VATPIC_CTR4(vatpic, "atpic master notify pin = %d "
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"(imr 0x%x irr 0x%x isr 0x%x)", pin,
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atpic->mask, atpic->request, atpic->service);
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/*
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* PIC interrupts are routed to both the Local APIC
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* and the I/O APIC to support operation in 1 of 3
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* modes.
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*
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* 1. Legacy PIC Mode: the PIC effectively bypasses
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* all APIC components. In mode '1' the local APIC is
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* disabled and LINT0 is reconfigured as INTR to
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* deliver the PIC interrupt directly to the CPU.
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*
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* 2. Virtual Wire Mode: the APIC is treated as a
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* virtual wire which delivers interrupts from the PIC
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* to the CPU. In mode '2' LINT0 is programmed as
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* ExtINT to indicate that the PIC is the source of
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* the interrupt.
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*
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* 3. Symmetric I/O Mode: PIC interrupts are fielded
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* by the I/O APIC and delivered to the appropriate
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* CPU. In mode '3' the I/O APIC input 0 is
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* programmed as ExtINT to indicate that the PIC is
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* the source of the interrupt.
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*/
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atpic->intr_raised = true;
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lapic_set_local_intr(vatpic->vm, -1, APIC_LVT_LINT0);
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vioapic_pulse_irq(vatpic->vm, 0);
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} else {
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VATPIC_CTR3(vatpic, "atpic master no eligible interrupts "
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"(imr 0x%x irr 0x%x isr 0x%x)",
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atpic->mask, atpic->request, atpic->service);
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}
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}
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static int
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vatpic_icw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
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{
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VATPIC_CTR1(vatpic, "atpic icw1 0x%x", val);
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atpic->ready = false;
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atpic->icw_num = 1;
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atpic->mask = 0;
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atpic->priority = 0;
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atpic->rd_cmd_reg = 0;
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if ((val & ICW1_SNGL) != 0) {
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VATPIC_CTR0(vatpic, "vatpic cascade mode required");
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return (-1);
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}
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if ((val & ICW1_IC4) == 0) {
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VATPIC_CTR0(vatpic, "vatpic icw4 required");
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return (-1);
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}
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atpic->icw_num++;
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return (0);
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}
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static int
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vatpic_icw2(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
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{
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VATPIC_CTR1(vatpic, "atpic icw2 0x%x", val);
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atpic->irq_base = val & 0xf8;
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atpic->icw_num++;
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return (0);
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}
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static int
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vatpic_icw3(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
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{
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VATPIC_CTR1(vatpic, "atpic icw3 0x%x", val);
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atpic->icw_num++;
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return (0);
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}
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static int
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vatpic_icw4(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
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{
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VATPIC_CTR1(vatpic, "atpic icw4 0x%x", val);
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if ((val & ICW4_8086) == 0) {
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VATPIC_CTR0(vatpic, "vatpic microprocessor mode required");
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return (-1);
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}
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if ((val & ICW4_AEOI) != 0)
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atpic->aeoi = true;
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atpic->icw_num = 0;
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atpic->ready = true;
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return (0);
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}
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static int
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vatpic_ocw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
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{
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VATPIC_CTR1(vatpic, "atpic ocw1 0x%x", val);
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atpic->mask = val & 0xff;
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return (0);
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}
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static int
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vatpic_ocw2(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
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{
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VATPIC_CTR1(vatpic, "atpic ocw2 0x%x", val);
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atpic->rotate = ((val & OCW2_R) != 0);
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if ((val & OCW2_EOI) != 0) {
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int isr_bit;
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if ((val & OCW2_SL) != 0) {
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/* specific EOI */
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isr_bit = val & 0x7;
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} else {
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/* non-specific EOI */
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isr_bit = vatpic_get_highest_isrpin(atpic);
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}
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if (isr_bit != -1) {
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atpic->service &= ~(1 << isr_bit);
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if (atpic->rotate)
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atpic->priority = isr_bit;
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}
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} else if ((val & OCW2_SL) != 0 && atpic->rotate == true) {
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/* specific priority */
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atpic->priority = val & 0x7;
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}
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return (0);
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}
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static int
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vatpic_ocw3(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
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{
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VATPIC_CTR1(vatpic, "atpic ocw3 0x%x", val);
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atpic->poll = ((val & OCW3_P) != 0);
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if (val & OCW3_RR) {
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/* read register command */
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atpic->rd_cmd_reg = val & OCW3_RIS;
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}
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return (0);
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}
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static void
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vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate)
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{
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struct atpic *atpic;
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int oldcnt, newcnt;
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bool level;
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KASSERT(pin >= 0 && pin < 16,
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("vatpic_set_pinstate: invalid pin number %d", pin));
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KASSERT(VATPIC_LOCKED(vatpic),
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("vatpic_set_pinstate: vatpic is not locked"));
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atpic = &vatpic->atpic[pin >> 3];
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oldcnt = atpic->acnt[pin & 0x7];
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if (newstate)
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atpic->acnt[pin & 0x7]++;
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else
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atpic->acnt[pin & 0x7]--;
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newcnt = atpic->acnt[pin & 0x7];
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if (newcnt < 0) {
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VATPIC_CTR2(vatpic, "atpic pin%d: bad acnt %d", pin, newcnt);
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}
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level = ((vatpic->elc[pin >> 3] & (1 << (pin & 0x7))) != 0);
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if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
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/* rising edge or level */
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VATPIC_CTR1(vatpic, "atpic pin%d: asserted", pin);
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atpic->request |= (1 << (pin & 0x7));
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} else if (oldcnt == 1 && newcnt == 0) {
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/* falling edge */
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VATPIC_CTR1(vatpic, "atpic pin%d: deasserted", pin);
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} else {
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VATPIC_CTR3(vatpic, "atpic pin%d: %s, ignored, acnt %d",
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pin, newstate ? "asserted" : "deasserted", newcnt);
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}
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vatpic_notify_intr(vatpic);
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}
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static int
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vatpic_set_irqstate(struct vm *vm, int irq, enum irqstate irqstate)
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{
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struct vatpic *vatpic;
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struct atpic *atpic;
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if (irq < 0 || irq > 15)
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return (EINVAL);
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vatpic = vm_atpic(vm);
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atpic = &vatpic->atpic[irq >> 3];
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if (atpic->ready == false)
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return (0);
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VATPIC_LOCK(vatpic);
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switch (irqstate) {
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case IRQSTATE_ASSERT:
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vatpic_set_pinstate(vatpic, irq, true);
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break;
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case IRQSTATE_DEASSERT:
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vatpic_set_pinstate(vatpic, irq, false);
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break;
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case IRQSTATE_PULSE:
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vatpic_set_pinstate(vatpic, irq, true);
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vatpic_set_pinstate(vatpic, irq, false);
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break;
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default:
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panic("vatpic_set_irqstate: invalid irqstate %d", irqstate);
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}
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VATPIC_UNLOCK(vatpic);
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return (0);
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}
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int
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vatpic_assert_irq(struct vm *vm, int irq)
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{
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return (vatpic_set_irqstate(vm, irq, IRQSTATE_ASSERT));
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}
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int
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vatpic_deassert_irq(struct vm *vm, int irq)
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{
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return (vatpic_set_irqstate(vm, irq, IRQSTATE_DEASSERT));
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}
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int
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vatpic_pulse_irq(struct vm *vm, int irq)
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{
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return (vatpic_set_irqstate(vm, irq, IRQSTATE_PULSE));
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}
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int
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vatpic_set_irq_trigger(struct vm *vm, int irq, enum vm_intr_trigger trigger)
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{
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struct vatpic *vatpic;
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if (irq < 0 || irq > 15)
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return (EINVAL);
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/*
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* See comment in vatpic_elc_handler. These IRQs must be
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* edge triggered.
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*/
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if (trigger == LEVEL_TRIGGER) {
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switch (irq) {
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case 0:
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case 1:
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case 2:
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case 8:
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case 13:
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return (EINVAL);
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}
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}
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vatpic = vm_atpic(vm);
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VATPIC_LOCK(vatpic);
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if (trigger == LEVEL_TRIGGER)
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vatpic->elc[irq >> 3] |= 1 << (irq & 0x7);
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else
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vatpic->elc[irq >> 3] &= ~(1 << (irq & 0x7));
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VATPIC_UNLOCK(vatpic);
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return (0);
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}
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void
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vatpic_pending_intr(struct vm *vm, int *vecptr)
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{
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struct vatpic *vatpic;
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struct atpic *atpic;
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int pin;
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vatpic = vm_atpic(vm);
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atpic = &vatpic->atpic[0];
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VATPIC_LOCK(vatpic);
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pin = vatpic_get_highest_irrpin(atpic);
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if (pin == -1)
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pin = 7;
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if (pin == 2) {
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atpic = &vatpic->atpic[1];
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pin = vatpic_get_highest_irrpin(atpic);
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}
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*vecptr = atpic->irq_base + pin;
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VATPIC_UNLOCK(vatpic);
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}
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static void
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vatpic_pin_accepted(struct atpic *atpic, int pin)
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{
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atpic->intr_raised = false;
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if (atpic->acnt[pin] == 0)
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atpic->request &= ~(1 << pin);
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if (atpic->aeoi == true) {
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if (atpic->rotate == true)
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|
atpic->priority = pin;
|
|
} else {
|
|
atpic->service |= (1 << pin);
|
|
}
|
|
}
|
|
|
|
void
|
|
vatpic_intr_accepted(struct vm *vm, int vector)
|
|
{
|
|
struct vatpic *vatpic;
|
|
int pin;
|
|
|
|
vatpic = vm_atpic(vm);
|
|
|
|
VATPIC_LOCK(vatpic);
|
|
|
|
pin = vector & 0x7;
|
|
|
|
if ((vector & ~0x7) == vatpic->atpic[1].irq_base) {
|
|
vatpic_pin_accepted(&vatpic->atpic[1], pin);
|
|
/*
|
|
* If this vector originated from the slave,
|
|
* accept the cascaded interrupt too.
|
|
*/
|
|
vatpic_pin_accepted(&vatpic->atpic[0], 2);
|
|
} else {
|
|
vatpic_pin_accepted(&vatpic->atpic[0], pin);
|
|
}
|
|
|
|
vatpic_notify_intr(vatpic);
|
|
|
|
VATPIC_UNLOCK(vatpic);
|
|
}
|
|
|
|
static int
|
|
vatpic_read(struct vatpic *vatpic, struct atpic *atpic, bool in, int port,
|
|
int bytes, uint32_t *eax)
|
|
{
|
|
VATPIC_LOCK(vatpic);
|
|
|
|
if (atpic->poll) {
|
|
VATPIC_CTR0(vatpic, "vatpic polled mode not supported");
|
|
VATPIC_UNLOCK(vatpic);
|
|
return (-1);
|
|
} else {
|
|
if (port & ICU_IMR_OFFSET) {
|
|
/* read interrrupt mask register */
|
|
*eax = atpic->mask;
|
|
} else {
|
|
if (atpic->rd_cmd_reg == OCW3_RIS) {
|
|
/* read interrupt service register */
|
|
*eax = atpic->service;
|
|
} else {
|
|
/* read interrupt request register */
|
|
*eax = atpic->request;
|
|
}
|
|
}
|
|
}
|
|
|
|
VATPIC_UNLOCK(vatpic);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
static int
|
|
vatpic_write(struct vatpic *vatpic, struct atpic *atpic, bool in, int port,
|
|
int bytes, uint32_t *eax)
|
|
{
|
|
int error;
|
|
uint8_t val;
|
|
|
|
error = 0;
|
|
val = *eax;
|
|
|
|
VATPIC_LOCK(vatpic);
|
|
|
|
if (port & ICU_IMR_OFFSET) {
|
|
if (atpic->ready) {
|
|
error = vatpic_ocw1(vatpic, atpic, val);
|
|
} else {
|
|
switch (atpic->icw_num) {
|
|
case 2:
|
|
error = vatpic_icw2(vatpic, atpic, val);
|
|
break;
|
|
case 3:
|
|
error = vatpic_icw3(vatpic, atpic, val);
|
|
break;
|
|
case 4:
|
|
error = vatpic_icw4(vatpic, atpic, val);
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
if (val & (1 << 4))
|
|
error = vatpic_icw1(vatpic, atpic, val);
|
|
|
|
if (atpic->ready) {
|
|
if (val & (1 << 3))
|
|
error = vatpic_ocw3(vatpic, atpic, val);
|
|
else
|
|
error = vatpic_ocw2(vatpic, atpic, val);
|
|
}
|
|
}
|
|
|
|
if (atpic->ready)
|
|
vatpic_notify_intr(vatpic);
|
|
|
|
VATPIC_UNLOCK(vatpic);
|
|
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
vatpic_master_handler(void *vm, int vcpuid, bool in, int port, int bytes,
|
|
uint32_t *eax)
|
|
{
|
|
struct vatpic *vatpic;
|
|
struct atpic *atpic;
|
|
|
|
vatpic = vm_atpic(vm);
|
|
atpic = &vatpic->atpic[0];
|
|
|
|
if (bytes != 1)
|
|
return (-1);
|
|
|
|
if (in) {
|
|
return (vatpic_read(vatpic, atpic, in, port, bytes, eax));
|
|
}
|
|
|
|
return (vatpic_write(vatpic, atpic, in, port, bytes, eax));
|
|
}
|
|
|
|
int
|
|
vatpic_slave_handler(void *vm, int vcpuid, bool in, int port, int bytes,
|
|
uint32_t *eax)
|
|
{
|
|
struct vatpic *vatpic;
|
|
struct atpic *atpic;
|
|
|
|
vatpic = vm_atpic(vm);
|
|
atpic = &vatpic->atpic[1];
|
|
|
|
if (bytes != 1)
|
|
return (-1);
|
|
|
|
if (in) {
|
|
return (vatpic_read(vatpic, atpic, in, port, bytes, eax));
|
|
}
|
|
|
|
return (vatpic_write(vatpic, atpic, in, port, bytes, eax));
|
|
}
|
|
|
|
int
|
|
vatpic_elc_handler(void *vm, int vcpuid, bool in, int port, int bytes,
|
|
uint32_t *eax)
|
|
{
|
|
struct vatpic *vatpic;
|
|
bool is_master;
|
|
|
|
vatpic = vm_atpic(vm);
|
|
is_master = (port == IO_ELCR1);
|
|
|
|
if (bytes != 1)
|
|
return (-1);
|
|
|
|
VATPIC_LOCK(vatpic);
|
|
|
|
if (in) {
|
|
if (is_master)
|
|
*eax = vatpic->elc[0];
|
|
else
|
|
*eax = vatpic->elc[1];
|
|
} else {
|
|
/*
|
|
* For the master PIC the cascade channel (IRQ2), the
|
|
* heart beat timer (IRQ0), and the keyboard
|
|
* controller (IRQ1) cannot be programmed for level
|
|
* mode.
|
|
*
|
|
* For the slave PIC the real time clock (IRQ8) and
|
|
* the floating point error interrupt (IRQ13) cannot
|
|
* be programmed for level mode.
|
|
*/
|
|
if (is_master)
|
|
vatpic->elc[0] = (*eax & 0xf8);
|
|
else
|
|
vatpic->elc[1] = (*eax & 0xde);
|
|
}
|
|
|
|
VATPIC_UNLOCK(vatpic);
|
|
|
|
return (0);
|
|
}
|
|
|
|
struct vatpic *
|
|
vatpic_init(struct vm *vm)
|
|
{
|
|
struct vatpic *vatpic;
|
|
|
|
vatpic = malloc(sizeof(struct vatpic), M_VATPIC, M_WAITOK | M_ZERO);
|
|
vatpic->vm = vm;
|
|
|
|
mtx_init(&vatpic->mtx, "vatpic lock", NULL, MTX_SPIN);
|
|
|
|
return (vatpic);
|
|
}
|
|
|
|
void
|
|
vatpic_cleanup(struct vatpic *vatpic)
|
|
{
|
|
free(vatpic, M_VATPIC);
|
|
}
|