353 lines
8.7 KiB
C
353 lines
8.7 KiB
C
/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
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/*-
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* Copyright (C) 2003-2004 Olivier Houchard
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#ifndef _LOCORE
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#include <sys/types.h>
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#ifndef I32_bit
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#define I32_bit (1 << 7) /* IRQ disable */
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#endif
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#ifndef F32_bit
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#define F32_bit (1 << 6) /* FIQ disable */
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#endif
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#define __with_interrupts_disabled(expr) \
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do { \
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u_int cpsr_save, tmp; \
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\
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__asm __volatile( \
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"mrs %0, cpsr;" \
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"orr %1, %0, %2;" \
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"msr cpsr_all, %1;" \
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: "=r" (cpsr_save), "=r" (tmp) \
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: "I" (I32_bit | F32_bit) \
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: "cc" ); \
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(expr); \
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__asm __volatile( \
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"msr cpsr_all, %0" \
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: /* no output */ \
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: "r" (cpsr_save) \
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: "cc" ); \
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} while(0)
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#define ARM_RAS_START 0xe0000004
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#define ARM_RAS_END 0xe0000008
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static __inline uint32_t
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__swp(uint32_t val, volatile uint32_t *ptr)
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{
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__asm __volatile("swp %0, %2, [%3]"
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: "=&r" (val), "=m" (*ptr)
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: "r" (val), "r" (ptr), "m" (*ptr)
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: "memory");
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return (val);
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}
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#ifdef _KERNEL
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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__with_interrupts_disabled(*address |= setmask);
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}
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
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{
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__with_interrupts_disabled(*address &= ~clearmask);
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}
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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int ret;
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__with_interrupts_disabled(
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{
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if (*p == cmpval) {
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*p = newval;
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ret = 1;
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} else {
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ret = 0;
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}
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});
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return (ret);
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}
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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__with_interrupts_disabled(*p += val);
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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__with_interrupts_disabled(*p -= val);
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}
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static __inline uint32_t
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atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
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{
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uint32_t value;
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__with_interrupts_disabled(
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{
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value = *p;
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*p += v;
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});
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return (value);
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}
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#else /* !_KERNEL */
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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register int done, ras_start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"cmp %1, %3\n"
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"streq %4, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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"moveq %1, #1\n"
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"movne %1, #0\n"
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: "=r" (ras_start), "=r" (done)
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,"+r" (p), "+r" (cmpval), "+r" (newval) : : "memory");
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return (done);
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}
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"add %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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: "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
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: : "memory");
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"sub %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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: "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
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: : "memory");
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}
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"orr %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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: "=r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
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: : "memory");
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}
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"bic %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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"mov %1, #0\n"
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"str %1, [%0]\n"
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: "=r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)
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: : "memory");
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}
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static __inline uint32_t
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atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
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{
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uint32_t ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"add %3, %1, %3\n"
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"str %3, [%2]\n"
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"2:\n"
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"mov %3, #0\n"
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"str %3, [%0]\n"
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: "=r" (ras_start), "=r" (start), "+r" (p), "+r" (v)
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: : "memory");
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return (start);
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}
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#endif /* _KERNEL */
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static __inline int
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atomic_load_32(volatile uint32_t *v)
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{
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return (*v);
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}
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static __inline void
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atomic_store_32(volatile uint32_t *dst, uint32_t src)
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{
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*dst = src;
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}
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static __inline uint32_t
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atomic_readandclear_32(volatile u_int32_t *p)
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{
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return (__swp(0, p));
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}
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#undef __with_interrupts_disabled
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#endif /* _LOCORE */
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static __inline int
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atomic_cmpset_long(volatile u_long *dst, u_long exp, u_long src)
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{
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return (atomic_cmpset_32((volatile u_int *)dst, (u_int)exp,
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(u_int)src));
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}
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#define atomic_set_rel_int atomic_set_32
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#define atomic_set_acq_long atomic_set_32
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#define atomic_set_int atomic_set_32
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#define atomic_readandclear_int atomic_readandclear_32
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#define atomic_clear_int atomic_clear_32
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#define atomic_clear_acq_long atomic_clear_32
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#define atomic_subtract_int atomic_subtract_32
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#define atomic_subtract_rel_int atomic_subtract_32
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#define atomic_subtract_rel_32 atomic_subtract_32
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#define atomic_subtract_acq_int atomic_subtract_32
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#define atomic_add_int atomic_add_32
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#define atomic_add_acq_long atomic_add_32
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#define atomic_add_rel_int atomic_add_32
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#define atomic_add_rel_32 atomic_add_32
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#define atomic_add_acq_int atomic_add_32
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#define atomic_cmpset_int atomic_cmpset_32
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#define atomic_cmpset_rel_int atomic_cmpset_32
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#define atomic_cmpset_rel_ptr atomic_cmpset_ptr
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#define atomic_cmpset_acq_int atomic_cmpset_32
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#define atomic_cmpset_acq_ptr atomic_cmpset_ptr
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#define atomic_cmpset_acq_long atomic_cmpset_long
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#define atomic_store_rel_ptr atomic_store_ptr
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#define atomic_store_rel_int atomic_store_32
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#define atomic_cmpset_rel_32 atomic_cmpset_32
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#define atomic_cmpset_rel_ptr atomic_cmpset_ptr
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#define atomic_load_acq_int atomic_load_32
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#define atomic_load_acq_32 atomic_load_32
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#define atomic_clear_ptr atomic_clear_32
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#define atomic_store_ptr atomic_store_32
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#define atomic_cmpset_ptr atomic_cmpset_32
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#define atomic_set_ptr atomic_set_32
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#define atomic_fetchadd_int atomic_fetchadd_32
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#endif /* _MACHINE_ATOMIC_H_ */
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