3be4cb0b4a
changes: 01 - Enhanced LRO: LRO feature is extended to support multi-buffer mode. Previously, Ethernet frames received in contiguous buffers were offloaded. Now, frames received in multiple non-contiguous buffers can be offloaded, as well. The driver now supports LRO for jumbo frames. 02 - Locks Optimization: The driver code was re-organized to limit the use of locks. Moreover, lock contention was reduced by replacing wait locks with try locks. 03 - Code Optimization: The driver code was re-factored to eliminate some memcpy operations. Fast path loops were optimized. 04 - Tag Creations: Physical Buffer Tags are now optimized based upon frame size. For better performance, Physical Memory Maps are now re-used. 05 - Configuration: Features such as TSO, LRO, and Interrupt Mode can be configured either at load or at run time. Rx buffer mode (mode 1 or mode 2) can be configured at load time through kenv. 06 - Driver Statistics: Run time statistics are enhanced to provide better visibility into the driver performance. 07 - Bug Fixes: The driver contains fixes for the problems discovered and reported since last submission. 08 - MSI support: Added Message Signaled Interrupt feature which currently uses 1 message. 09 Removed feature: Rx 3 buffer mode feature has been removed. Driver now supports 1, 2 and 5 buffer modes of which 2 and 5 buffer modes can be used for header separation. 10 Compiler warning: Fixed compiler warning when compiled for 32 bit system. 11 Copyright notice: Source files are updated with the proper copyright notice. MFC after: 3 days Submitted by: Alicia Pena <Alicia dot Pena at neterion dot com>, Muhammad Shafiq <Muhammad dot Shafiq at neterion dot com>
295 lines
10 KiB
C
295 lines
10 KiB
C
/*-
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* Copyright (c) 2002-2007 Neterion, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifdef XGE_DEBUG_FP
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#include <dev/nxge/include/xgehal-channel.h>
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#endif
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
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__hal_channel_dtr_alloc(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh)
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{
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void **tmp_arr;
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ)
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unsigned long flags = 0;
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#endif
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if (channel->terminating) {
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return XGE_HAL_FAIL;
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}
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if (channel->reserve_length - channel->reserve_top >
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channel->reserve_threshold) {
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_alloc_after_swap:
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*dtrh = channel->reserve_arr[--channel->reserve_length];
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xge_debug_channel(XGE_TRACE, "dtrh 0x"XGE_OS_LLXFMT" allocated, "
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"channel %d:%d:%d, reserve_idx %d",
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(unsigned long long)(ulong_t)*dtrh,
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channel->type, channel->post_qid,
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channel->compl_qid, channel->reserve_length);
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return XGE_HAL_OK;
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}
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#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ)
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xge_os_spin_lock_irq(&channel->free_lock, flags);
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#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE)
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xge_os_spin_lock(&channel->free_lock);
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#endif
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/* switch between empty and full arrays */
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/* the idea behind such a design is that by having free and reserved
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* arrays separated we basically separated irq and non-irq parts.
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* i.e. no additional lock need to be done when we free a resource */
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if (channel->reserve_initial - channel->free_length >
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channel->reserve_threshold) {
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tmp_arr = channel->reserve_arr;
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channel->reserve_arr = channel->free_arr;
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channel->reserve_length = channel->reserve_initial;
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channel->free_arr = tmp_arr;
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channel->reserve_top = channel->free_length;
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channel->free_length = channel->reserve_initial;
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channel->stats.reserve_free_swaps_cnt++;
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xge_debug_channel(XGE_TRACE,
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"switch on channel %d:%d:%d, reserve_length %d, "
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"free_length %d", channel->type, channel->post_qid,
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channel->compl_qid, channel->reserve_length,
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channel->free_length);
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#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ)
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xge_os_spin_unlock_irq(&channel->free_lock, flags);
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#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE)
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xge_os_spin_unlock(&channel->free_lock);
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#endif
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goto _alloc_after_swap;
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}
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#if defined(XGE_HAL_RX_MULTI_FREE_IRQ) || defined(XGE_HAL_TX_MULTI_FREE_IRQ)
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xge_os_spin_unlock_irq(&channel->free_lock, flags);
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#elif defined(XGE_HAL_RX_MULTI_FREE) || defined(XGE_HAL_TX_MULTI_FREE)
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xge_os_spin_unlock(&channel->free_lock);
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#endif
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xge_debug_channel(XGE_TRACE, "channel %d:%d:%d is empty!",
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channel->type, channel->post_qid,
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channel->compl_qid);
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channel->stats.full_cnt++;
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*dtrh = NULL;
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return XGE_HAL_INF_OUT_OF_DESCRIPTORS;
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}
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_channel_dtr_restore(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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int offset)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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/* restore a previously allocated dtrh at current offset and update
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* the available reserve length accordingly. If dtrh is null just
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* update the reserve length, only */
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if (dtrh) {
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channel->reserve_arr[channel->reserve_length + offset] = dtrh;
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xge_debug_channel(XGE_TRACE, "dtrh 0x"XGE_OS_LLXFMT" restored for "
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"channel %d:%d:%d, offset %d at reserve index %d, ",
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(unsigned long long)(ulong_t)dtrh, channel->type,
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channel->post_qid, channel->compl_qid, offset,
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channel->reserve_length + offset);
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}
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else {
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channel->reserve_length += offset;
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xge_debug_channel(XGE_TRACE, "channel %d:%d:%d, restored "
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"for offset %d, new reserve_length %d, free length %d",
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channel->type, channel->post_qid, channel->compl_qid,
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offset, channel->reserve_length, channel->free_length);
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}
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}
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_channel_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t*)channelh;
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xge_assert(channel->work_arr[channel->post_index] == NULL);
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channel->work_arr[channel->post_index++] = dtrh;
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/* wrap-around */
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if (channel->post_index == channel->length)
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channel->post_index = 0;
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}
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_channel_dtr_try_complete(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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xge_assert(channel->work_arr);
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xge_assert(channel->compl_index < channel->length);
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*dtrh = channel->work_arr[channel->compl_index];
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}
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_channel_dtr_complete(xge_hal_channel_h channelh)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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channel->work_arr[channel->compl_index] = NULL;
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/* wrap-around */
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if (++channel->compl_index == channel->length)
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channel->compl_index = 0;
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channel->stats.total_compl_cnt++;
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}
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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__hal_channel_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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channel->free_arr[--channel->free_length] = dtrh;
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xge_debug_channel(XGE_TRACE, "dtrh 0x"XGE_OS_LLXFMT" freed, "
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"channel %d:%d:%d, new free_length %d",
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(unsigned long long)(ulong_t)dtrh,
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channel->type, channel->post_qid,
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channel->compl_qid, channel->free_length);
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}
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/**
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* xge_hal_channel_dtr_count
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* @channelh: Channel handle. Obtained via xge_hal_channel_open().
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*
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* Retreive number of DTRs available. This function can not be called
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* from data path.
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
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xge_hal_channel_dtr_count(xge_hal_channel_h channelh)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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return ((channel->reserve_length - channel->reserve_top) +
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(channel->reserve_initial - channel->free_length) -
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channel->reserve_threshold);
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}
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/**
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* xge_hal_channel_userdata - Get user-specified channel context.
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* @channelh: Channel handle. Obtained via xge_hal_channel_open().
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*
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* Returns: per-channel "user data", which can be any ULD-defined context.
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* The %userdata "gets" into the channel at open time
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* (see xge_hal_channel_open()).
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*
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* See also: xge_hal_channel_open().
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void*
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xge_hal_channel_userdata(xge_hal_channel_h channelh)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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return channel->userdata;
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}
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/**
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* xge_hal_channel_id - Get channel ID.
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* @channelh: Channel handle. Obtained via xge_hal_channel_open().
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*
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* Returns: channel ID. For link layer channel id is the number
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* in the range from 0 to 7 that identifies hardware ring or fifo,
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* depending on the channel type.
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
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xge_hal_channel_id(xge_hal_channel_h channelh)
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{
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xge_hal_channel_t *channel = (xge_hal_channel_t *)channelh;
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return channel->post_qid;
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}
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/**
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* xge_hal_check_alignment - Check buffer alignment and calculate the
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* "misaligned" portion.
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* @dma_pointer: DMA address of the buffer.
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* @size: Buffer size, in bytes.
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* @alignment: Alignment "granularity" (see below), in bytes.
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* @copy_size: Maximum number of bytes to "extract" from the buffer
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* (in order to spost it as a separate scatter-gather entry). See below.
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*
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* Check buffer alignment and calculate "misaligned" portion, if exists.
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* The buffer is considered aligned if its address is multiple of
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* the specified @alignment. If this is the case,
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* xge_hal_check_alignment() returns zero.
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* Otherwise, xge_hal_check_alignment() uses the last argument,
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* @copy_size,
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* to calculate the size to "extract" from the buffer. The @copy_size
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* may or may not be equal @alignment. The difference between these two
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* arguments is that the @alignment is used to make the decision: aligned
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* or not aligned. While the @copy_size is used to calculate the portion
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* of the buffer to "extract", i.e. to post as a separate entry in the
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* transmit descriptor. For example, the combination
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* @alignment=8 and @copy_size=64 will work okay on AMD Opteron boxes.
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*
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* Note: @copy_size should be a multiple of @alignment. In many practical
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* cases @copy_size and @alignment will probably be equal.
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*
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* See also: xge_hal_fifo_dtr_buffer_set_aligned().
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
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xge_hal_check_alignment(dma_addr_t dma_pointer, int size, int alignment,
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int copy_size)
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{
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int misaligned_size;
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misaligned_size = (int)(dma_pointer & (alignment - 1));
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if (!misaligned_size) {
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return 0;
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}
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if (size > copy_size) {
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misaligned_size = (int)(dma_pointer & (copy_size - 1));
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misaligned_size = copy_size - misaligned_size;
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} else {
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misaligned_size = size;
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}
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return misaligned_size;
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}
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