718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
398 lines
12 KiB
C
398 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_cmd_ch_attach(device_t dev);
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static int ata_cmd_status(device_t dev);
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static int ata_cmd_setmode(device_t dev, int target, int mode);
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static int ata_sii_ch_attach(device_t dev);
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static int ata_sii_ch_detach(device_t dev);
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static int ata_sii_status(device_t dev);
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static void ata_sii_reset(device_t dev);
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static int ata_sii_setmode(device_t dev, int target, int mode);
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/* misc defines */
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#define SII_MEMIO 1
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#define SII_INTR 0x01
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#define SII_SETCLK 0x02
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#define SII_BUG 0x04
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#define SII_4CH 0x08
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/*
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* Silicon Image Inc. (SiI) (former CMD) chipset support functions
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*/
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static int
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ata_sii_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static const struct ata_chip_id ids[] =
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{{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
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{ ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
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{ ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
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{ ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
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{ ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
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{ ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
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{ ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
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{ ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
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{ ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
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{ ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
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{ ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
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{ ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
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{ 0, 0, 0, 0, 0, 0}};
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if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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ctlr->chipinit = ata_sii_chipinit;
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return (BUS_PROBE_LOW_PRIORITY);
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}
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int
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ata_sii_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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switch (ctlr->chip->cfg1) {
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case SII_MEMIO:
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE))){
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if (ctlr->chip->chipid != ATA_SII0680 ||
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(pci_read_config(dev, 0x8a, 1) & 1))
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return ENXIO;
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}
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if (ctlr->chip->cfg2 & SII_SETCLK) {
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if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
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pci_write_config(dev, 0x8a,
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(pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
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if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
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device_printf(dev, "%s could not set ATA133 clock\n",
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ctlr->chip->text);
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}
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/* if we have 4 channels enable the second set */
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if (ctlr->chip->cfg2 & SII_4CH) {
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ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
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ctlr->channels = 4;
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}
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/* dont block interrupts from any channel */
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pci_write_config(dev, 0x48,
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(pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
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/* enable PCI interrupt as BIOS might not */
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pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
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if (ctlr->r_res2) {
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ctlr->ch_attach = ata_sii_ch_attach;
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ctlr->ch_detach = ata_sii_ch_detach;
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}
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if (ctlr->chip->max_dma >= ATA_SA150) {
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ctlr->reset = ata_sii_reset;
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ctlr->setmode = ata_sata_setmode;
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ctlr->getrev = ata_sata_getrev;
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}
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else
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ctlr->setmode = ata_sii_setmode;
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break;
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default:
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if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
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device_printf(dev, "HW has secondary channel disabled\n");
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ctlr->channels = 1;
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}
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/* enable interrupt as BIOS might not */
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pci_write_config(dev, 0x71, 0x01, 1);
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ctlr->ch_attach = ata_cmd_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->setmode = ata_cmd_setmode;
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break;
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}
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return 0;
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}
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static int
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ata_cmd_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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/* setup the usual register normal pci style */
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if (ata_pci_ch_attach(dev))
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return ENXIO;
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if (ctlr->chip->cfg2 & SII_INTR)
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ch->hw.status = ata_cmd_status;
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ch->flags |= ATA_NO_ATAPI_DMA;
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return 0;
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}
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static int
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ata_cmd_status(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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u_int8_t reg71;
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if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
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(ch->unit ? 0x08 : 0x04))) {
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pci_write_config(device_get_parent(dev), 0x71,
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reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
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return ata_pci_status(dev);
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}
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return 0;
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}
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static int
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ata_cmd_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int devno = (ch->unit << 1) + target;
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int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
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int ureg = ch->unit ? 0x7b : 0x73;
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int piomode;
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static const uint8_t piotimings[] =
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{ 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
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static const uint8_t udmatimings[][2] =
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{ { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 },
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{ 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } };
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mode = min(mode, ctlr->chip->max_dma);
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if (mode >= ATA_UDMA0) {
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u_int8_t umode = pci_read_config(parent, ureg, 1);
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umode &= ~(target == 0 ? 0x35 : 0xca);
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umode |= udmatimings[mode & ATA_MODE_MASK][target];
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pci_write_config(parent, ureg, umode, 1);
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piomode = ATA_PIO4;
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} else {
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pci_write_config(parent, ureg,
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pci_read_config(parent, ureg, 1) &
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~(target == 0 ? 0x35 : 0xca), 1);
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piomode = mode;
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}
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pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
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return (mode);
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}
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static int
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ata_sii_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
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int i;
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for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
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ch->r_io[i].res = ctlr->r_res2;
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ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
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}
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ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
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ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
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ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
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ata_default_registers(dev);
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ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
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ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
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ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
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ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
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ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
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ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
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if (ctlr->chip->max_dma >= ATA_SA150) {
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
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ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
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ch->r_io[ATA_SERROR].res = ctlr->r_res2;
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ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
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ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
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ch->flags |= ATA_NO_SLAVE;
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ch->flags |= ATA_SATA;
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ch->flags |= ATA_KNOWN_PRESENCE;
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/* enable PHY state change interrupt */
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ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
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}
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if (ctlr->chip->cfg2 & SII_BUG) {
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/* work around errata in early chips */
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ch->dma.boundary = 8192;
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ch->dma.segsize = 15 * DEV_BSIZE;
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}
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ata_pci_hw(dev);
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ch->hw.status = ata_sii_status;
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if (ctlr->chip->cfg2 & SII_SETCLK)
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ch->flags |= ATA_CHECKS_CABLE;
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ata_pci_dmainit(dev);
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return 0;
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}
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static int
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ata_sii_ch_detach(device_t dev)
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{
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ata_pci_dmafini(dev);
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return (0);
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}
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static int
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ata_sii_status(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
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int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
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/* do we have any PHY events ? */
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if (ctlr->chip->max_dma >= ATA_SA150 &&
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(ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
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ata_sata_phy_check_events(dev, -1);
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if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
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return ata_pci_status(dev);
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else
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return 0;
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}
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static void
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ata_sii_reset(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
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uint32_t val;
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/* Apply R_ERR on DMA activate FIS errata workaround. */
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val = ATA_INL(ctlr->r_res2, 0x14c + offset);
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if ((val & 0x3) == 0x1)
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ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
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if (ata_sata_phy_reset(dev, -1, 1))
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ata_generic_reset(dev);
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else
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ch->devices = 0;
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}
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static int
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ata_sii_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int rego = (ch->unit << 4) + (target << 1);
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int mreg = ch->unit ? 0x84 : 0x80;
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int mask = 0x03 << (target << 2);
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int mval = pci_read_config(parent, mreg, 1) & ~mask;
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int piomode;
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u_int8_t preg = 0xa4 + rego;
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u_int8_t dreg = 0xa8 + rego;
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u_int8_t ureg = 0xac + rego;
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static const uint16_t piotimings[] =
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{ 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
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static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
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static const uint8_t udmatimings[] =
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{ 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
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mode = min(mode, ctlr->chip->max_dma);
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if (ctlr->chip->cfg2 & SII_SETCLK) {
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if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
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(pci_read_config(parent, 0x79, 1) &
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(ch->unit ? 0x02 : 0x01))) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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}
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if (mode >= ATA_UDMA0) {
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pci_write_config(parent, mreg,
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mval | (0x03 << (target << 2)), 1);
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pci_write_config(parent, ureg,
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(pci_read_config(parent, ureg, 1) & ~0x3f) |
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udmatimings[mode & ATA_MODE_MASK], 1);
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piomode = ATA_PIO4;
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} else if (mode >= ATA_WDMA0) {
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pci_write_config(parent, mreg,
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mval | (0x02 << (target << 2)), 1);
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pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
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piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
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(mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
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} else {
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pci_write_config(parent, mreg,
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mval | (0x01 << (target << 2)), 1);
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piomode = mode;
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}
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pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
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return (mode);
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}
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ATA_DECLARE_DRIVER(ata_sii);
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