d1ce910572
takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
597 lines
18 KiB
C
597 lines
18 KiB
C
/*
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* Copyright (c) 1997, 1998
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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struct tl_type {
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u_int16_t tl_vid;
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u_int16_t tl_did;
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char *tl_name;
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};
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/*
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* ThunderLAN TX/RX list format. The TX and RX lists are pretty much
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* identical: the list begins with a 32-bit forward pointer which points
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* at the next list in the chain, followed by 16 bits for the total
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* frame size, and a 16 bit status field. This is followed by a series
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* of 10 32-bit data count/data address pairs that point to the fragments
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* that make up the complete frame.
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*/
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#define TL_MAXFRAGS 10
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#define TL_RX_LIST_CNT 64
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#define TL_TX_LIST_CNT 128
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#define TL_MIN_FRAMELEN 64
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struct tl_frag {
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u_int32_t tlist_dcnt;
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u_int32_t tlist_dadr;
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};
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struct tl_list {
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u_int32_t tlist_fptr; /* phys address of next list */
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u_int16_t tlist_cstat; /* status word */
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u_int16_t tlist_frsize; /* size of data in frame */
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struct tl_frag tl_frag[TL_MAXFRAGS];
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};
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/*
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* This is a special case of an RX list. By setting the One_Frag
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* bit in the NETCONFIG register, the driver can force the ThunderLAN
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* chip to use only one fragment when DMAing RX frames.
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*/
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struct tl_list_onefrag {
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u_int32_t tlist_fptr;
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u_int16_t tlist_cstat;
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u_int16_t tlist_frsize;
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struct tl_frag tl_frag;
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};
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struct tl_list_data {
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struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT];
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struct tl_list tl_tx_list[TL_TX_LIST_CNT];
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unsigned char tl_pad[TL_MIN_FRAMELEN];
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};
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struct tl_chain {
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struct tl_list *tl_ptr;
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struct mbuf *tl_mbuf;
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struct tl_chain *tl_next;
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};
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struct tl_chain_onefrag {
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struct tl_list_onefrag *tl_ptr;
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struct mbuf *tl_mbuf;
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struct tl_chain_onefrag *tl_next;
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};
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struct tl_chain_data {
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struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT];
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struct tl_chain tl_tx_chain[TL_TX_LIST_CNT];
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struct tl_chain_onefrag *tl_rx_head;
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struct tl_chain_onefrag *tl_rx_tail;
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struct tl_chain *tl_tx_head;
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struct tl_chain *tl_tx_tail;
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struct tl_chain *tl_tx_free;
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};
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struct tl_softc {
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struct arpcom arpcom; /* interface info */
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struct ifmedia ifmedia; /* media info */
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bus_space_handle_t tl_bhandle;
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bus_space_tag_t tl_btag;
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void *tl_intrhand;
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struct resource *tl_irq;
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struct resource *tl_res;
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device_t tl_miibus;
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struct tl_type *tl_dinfo; /* ThunderLAN adapter info */
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u_int8_t tl_unit; /* interface number */
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u_int8_t tl_eeaddr;
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struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */
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struct tl_chain_data tl_cdata;
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u_int8_t tl_txeoc;
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u_int8_t tl_bitrate;
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int tl_if_flags;
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struct callout_handle tl_stat_ch;
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struct mtx tl_mtx;
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};
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#define TL_LOCK(_sc) mtx_enter(&(_sc)->tl_mtx, MTX_DEF)
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#define TL_UNLOCK(_sc) mtx_exit(&(_sc)->tl_mtx, MTX_DEF)
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/*
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* Transmit interrupt threshold.
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*/
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#define TX_THR 0x00000004
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/*
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* General constants that are fun to know.
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*
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* The ThunderLAN controller is made by Texas Instruments. The
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* manual indicates that if the EEPROM checksum fails, the PCI
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* vendor and device ID registers will be loaded with TI-specific
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* values.
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*/
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#define TI_VENDORID 0x104C
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#define TI_DEVICEID_THUNDERLAN 0x0500
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/*
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* These are the PCI vendor and device IDs for Compaq ethernet
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* adapters based on the ThunderLAN controller.
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*/
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#define COMPAQ_VENDORID 0x0E11
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#define COMPAQ_DEVICEID_NETEL_10_100 0xAE32
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#define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33
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#define COMPAQ_DEVICEID_NETEL_10 0xAE34
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#define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35
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#define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40
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#define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43
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#define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011
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#define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012
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#define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030
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#define COMPAQ_DEVICEID_NETFLEX_3P 0xF130
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#define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150
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/*
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* These are the PCI vendor and device IDs for Olicom
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* adapters based on the ThunderLAN controller.
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*/
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#define OLICOM_VENDORID 0x108D
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#define OLICOM_DEVICEID_OC2183 0x0013
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#define OLICOM_DEVICEID_OC2325 0x0012
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#define OLICOM_DEVICEID_OC2326 0x0014
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/*
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* PCI low memory base and low I/O base
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*/
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#define TL_PCI_LOIO 0x10
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#define TL_PCI_LOMEM 0x14
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/*
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* PCI latency timer (it's actually 0x0D, but we want a value
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* that's longword aligned).
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*/
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#define TL_PCI_LATENCY_TIMER 0x0C
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#define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */
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#define TL_DIO_RAM_SEL 0x4000 /* RAM address select */
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#define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */
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/*
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* Interrupt types
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*/
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#define TL_INTR_INVALID 0x0
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#define TL_INTR_TXEOF 0x1
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#define TL_INTR_STATOFLOW 0x2
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#define TL_INTR_RXEOF 0x3
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#define TL_INTR_DUMMY 0x4
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#define TL_INTR_TXEOC 0x5
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#define TL_INTR_ADCHK 0x6
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#define TL_INTR_RXEOC 0x7
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#define TL_INT_MASK 0x001C
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#define TL_VEC_MASK 0x1FE0
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/*
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* Host command register bits
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*/
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#define TL_CMD_GO 0x80000000
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#define TL_CMD_STOP 0x40000000
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#define TL_CMD_ACK 0x20000000
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#define TL_CMD_CHSEL7 0x10000000
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#define TL_CMD_CHSEL6 0x08000000
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#define TL_CMD_CHSEL5 0x04000000
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#define TL_CMD_CHSEL4 0x02000000
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#define TL_CMD_CHSEL3 0x01000000
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#define TL_CMD_CHSEL2 0x00800000
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#define TL_CMD_CHSEL1 0x00400000
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#define TL_CMD_CHSEL0 0x00200000
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#define TL_CMD_EOC 0x00100000
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#define TL_CMD_RT 0x00080000
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#define TL_CMD_NES 0x00040000
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#define TL_CMD_ZERO0 0x00020000
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#define TL_CMD_ZERO1 0x00010000
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#define TL_CMD_ADRST 0x00008000
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#define TL_CMD_LDTMR 0x00004000
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#define TL_CMD_LDTHR 0x00002000
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#define TL_CMD_REQINT 0x00001000
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#define TL_CMD_INTSOFF 0x00000800
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#define TL_CMD_INTSON 0x00000400
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#define TL_CMD_RSVD0 0x00000200
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#define TL_CMD_RSVD1 0x00000100
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#define TL_CMD_ACK7 0x00000080
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#define TL_CMD_ACK6 0x00000040
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#define TL_CMD_ACK5 0x00000020
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#define TL_CMD_ACK4 0x00000010
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#define TL_CMD_ACK3 0x00000008
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#define TL_CMD_ACK2 0x00000004
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#define TL_CMD_ACK1 0x00000002
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#define TL_CMD_ACK0 0x00000001
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#define TL_CMD_CHSEL_MASK 0x01FE0000
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#define TL_CMD_ACK_MASK 0xFF
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/*
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* EEPROM address where station address resides.
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*/
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#define TL_EEPROM_EADDR 0x83
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#define TL_EEPROM_EADDR2 0x99
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#define TL_EEPROM_EADDR3 0xAF
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#define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different
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address than Compaqs. */
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/*
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* ThunderLAN host command register offsets.
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* (Can be accessed either by IO ports or memory map.)
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*/
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#define TL_HOSTCMD 0x00
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#define TL_CH_PARM 0x04
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#define TL_DIO_ADDR 0x08
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#define TL_HOST_INT 0x0A
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#define TL_DIO_DATA 0x0C
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/*
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* ThunderLAN internal registers
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*/
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#define TL_NETCMD 0x00
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#define TL_NETSIO 0x01
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#define TL_NETSTS 0x02
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#define TL_NETMASK 0x03
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#define TL_NETCONFIG 0x04
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#define TL_MANTEST 0x06
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#define TL_VENID_LSB 0x08
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#define TL_VENID_MSB 0x09
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#define TL_DEVID_LSB 0x0A
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#define TL_DEVID_MSB 0x0B
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#define TL_REVISION 0x0C
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#define TL_SUBCLASS 0x0D
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#define TL_MINLAT 0x0E
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#define TL_MAXLAT 0x0F
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#define TL_AREG0_B5 0x10
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#define TL_AREG0_B4 0x11
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#define TL_AREG0_B3 0x12
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#define TL_AREG0_B2 0x13
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#define TL_AREG0_B1 0x14
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#define TL_AREG0_B0 0x15
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#define TL_AREG1_B5 0x16
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#define TL_AREG1_B4 0x17
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#define TL_AREG1_B3 0x18
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#define TL_AREG1_B2 0x19
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#define TL_AREG1_B1 0x1A
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#define TL_AREG1_B0 0x1B
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#define TL_AREG2_B5 0x1C
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#define TL_AREG2_B4 0x1D
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#define TL_AREG2_B3 0x1E
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#define TL_AREG2_B2 0x1F
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#define TL_AREG2_B1 0x20
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#define TL_AREG2_B0 0x21
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#define TL_AREG3_B5 0x22
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#define TL_AREG3_B4 0x23
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#define TL_AREG3_B3 0x24
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#define TL_AREG3_B2 0x25
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#define TL_AREG3_B1 0x26
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#define TL_AREG3_B0 0x27
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#define TL_HASH1 0x28
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#define TL_HASH2 0x2C
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#define TL_TXGOODFRAMES 0x30
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#define TL_TXUNDERRUN 0x33
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#define TL_RXGOODFRAMES 0x34
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#define TL_RXOVERRUN 0x37
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#define TL_DEFEREDTX 0x38
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#define TL_CRCERROR 0x3A
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#define TL_CODEERROR 0x3B
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#define TL_MULTICOLTX 0x3C
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#define TL_SINGLECOLTX 0x3E
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#define TL_EXCESSIVECOL 0x40
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#define TL_LATECOL 0x41
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#define TL_CARRIERLOSS 0x42
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#define TL_ACOMMIT 0x43
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#define TL_LDREG 0x44
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#define TL_BSIZEREG 0x45
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#define TL_MAXRX 0x46
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/*
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* ThunderLAN SIO register bits
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*/
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#define TL_SIO_MINTEN 0x80
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#define TL_SIO_ECLOK 0x40
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#define TL_SIO_ETXEN 0x20
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#define TL_SIO_EDATA 0x10
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#define TL_SIO_NMRST 0x08
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#define TL_SIO_MCLK 0x04
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#define TL_SIO_MTXEN 0x02
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#define TL_SIO_MDATA 0x01
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/*
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* Thunderlan NETCONFIG bits
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*/
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#define TL_CFG_RCLKTEST 0x8000
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#define TL_CFG_TCLKTEST 0x4000
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#define TL_CFG_BITRATE 0x2000
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#define TL_CFG_RXCRC 0x1000
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#define TL_CFG_PEF 0x0800
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#define TL_CFG_ONEFRAG 0x0400
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#define TL_CFG_ONECHAN 0x0200
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#define TL_CFG_MTEST 0x0100
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#define TL_CFG_PHYEN 0x0080
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#define TL_CFG_MACSEL6 0x0040
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#define TL_CFG_MACSEL5 0x0020
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#define TL_CFG_MACSEL4 0x0010
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#define TL_CFG_MACSEL3 0x0008
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#define TL_CFG_MACSEL2 0x0004
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#define TL_CFG_MACSEL1 0x0002
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#define TL_CFG_MACSEL0 0x0001
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/*
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* ThunderLAN NETSTS bits
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*/
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#define TL_STS_MIRQ 0x80
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#define TL_STS_HBEAT 0x40
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#define TL_STS_TXSTOP 0x20
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#define TL_STS_RXSTOP 0x10
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/*
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* ThunderLAN NETCMD bits
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*/
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#define TL_CMD_NRESET 0x80
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#define TL_CMD_NWRAP 0x40
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#define TL_CMD_CSF 0x20
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#define TL_CMD_CAF 0x10
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#define TL_CMD_NOBRX 0x08
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#define TL_CMD_DUPLEX 0x04
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#define TL_CMD_TRFRAM 0x02
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#define TL_CMD_TXPACE 0x01
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/*
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* ThunderLAN NETMASK bits
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*/
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#define TL_MASK_MASK7 0x80
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#define TL_MASK_MASK6 0x40
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#define TL_MASK_MASK5 0x20
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#define TL_MASK_MASK4 0x10
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/*
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* MII frame format
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*/
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#ifdef ANSI_DOESNT_ALLOW_BITFIELDS
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struct tl_mii_frame {
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u_int16_t mii_stdelim:2,
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mii_opcode:2,
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mii_phyaddr:5,
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mii_regaddr:5,
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mii_turnaround:2;
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u_int16_t mii_data;
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};
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#else
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struct tl_mii_frame {
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u_int8_t mii_stdelim;
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u_int8_t mii_opcode;
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u_int8_t mii_phyaddr;
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u_int8_t mii_regaddr;
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u_int8_t mii_turnaround;
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u_int16_t mii_data;
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};
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#endif
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/*
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* MII constants
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*/
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#define TL_MII_STARTDELIM 0x01
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#define TL_MII_READOP 0x02
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#define TL_MII_WRITEOP 0x01
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#define TL_MII_TURNAROUND 0x02
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#define TL_LAST_FRAG 0x80000000
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#define TL_CSTAT_UNUSED 0x8000
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#define TL_CSTAT_FRAMECMP 0x4000
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#define TL_CSTAT_READY 0x3000
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#define TL_CSTAT_UNUSED13 0x2000
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#define TL_CSTAT_UNUSED12 0x1000
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#define TL_CSTAT_EOC 0x0800
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#define TL_CSTAT_RXERROR 0x0400
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#define TL_CSTAT_PASSCRC 0x0200
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#define TL_CSTAT_DPRIO 0x0100
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#define TL_FRAME_MASK 0x00FFFFFF
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#define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK)
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#define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24)
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#define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK)
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#define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24)
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struct tl_stats {
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u_int32_t tl_txstat;
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u_int32_t tl_rxstat;
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u_int16_t tl_deferred;
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u_int8_t tl_crc_errors;
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u_int8_t tl_code_errors;
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u_int16_t tl_tx_multi_collision;
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u_int16_t tl_tx_single_collision;
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u_int8_t tl_excessive_collision;
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u_int8_t tl_late_collision;
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u_int8_t tl_carrier_loss;
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u_int8_t acommit;
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};
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/*
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* ACOMMIT register bits. These are used only when a bitrate
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* PHY is selected ('bitrate' bit in netconfig register is set).
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*/
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#define TL_AC_MTXER 0x01 /* reserved */
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#define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */
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#define TL_AC_MTXD2 0x04 /* loopback disable */
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#define TL_AC_MTXD3 0x08 /* full duplex disable */
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|
|
|
#define TL_AC_TXTHRESH 0xF0
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|
#define TL_AC_TXTHRESH_16LONG 0x00
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|
#define TL_AC_TXTHRESH_32LONG 0x10
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#define TL_AC_TXTHRESH_64LONG 0x20
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#define TL_AC_TXTHRESH_128LONG 0x30
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|
#define TL_AC_TXTHRESH_256LONG 0x40
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|
#define TL_AC_TXTHRESH_WHOLEPKT 0x50
|
|
|
|
/*
|
|
* PCI burst size register (TL_BSIZEREG).
|
|
*/
|
|
#define TL_RXBURST 0x0F
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|
#define TL_TXBURST 0xF0
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|
|
|
#define TL_RXBURST_4LONG 0x00
|
|
#define TL_RXBURST_8LONG 0x01
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|
#define TL_RXBURST_16LONG 0x02
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|
#define TL_RXBURST_32LONG 0x03
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|
#define TL_RXBURST_64LONG 0x04
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|
#define TL_RXBURST_128LONG 0x05
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|
|
|
#define TL_TXBURST_4LONG 0x00
|
|
#define TL_TXBURST_8LONG 0x10
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|
#define TL_TXBURST_16LONG 0x20
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|
#define TL_TXBURST_32LONG 0x30
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|
#define TL_TXBURST_64LONG 0x40
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|
#define TL_TXBURST_128LONG 0x50
|
|
|
|
/*
|
|
* register space access macros
|
|
*/
|
|
#define CSR_WRITE_4(sc, reg, val) \
|
|
bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
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|
#define CSR_WRITE_2(sc, reg, val) \
|
|
bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
|
|
#define CSR_WRITE_1(sc, reg, val) \
|
|
bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
|
|
|
|
#define CSR_READ_4(sc, reg) \
|
|
bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)
|
|
#define CSR_READ_2(sc, reg) \
|
|
bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)
|
|
#define CSR_READ_1(sc, reg) \
|
|
bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)
|
|
|
|
#define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x)
|
|
#define CMD_SET(sc, x) \
|
|
CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
|
|
#define CMD_CLR(sc, x) \
|
|
CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))
|
|
|
|
/*
|
|
* ThunderLAN adapters typically have a serial EEPROM containing
|
|
* configuration information. The main reason we're interested in
|
|
* it is because it also contains the adapters's station address.
|
|
*
|
|
* Access to the EEPROM is a bit goofy since it is a serial device:
|
|
* you have to do reads and writes one bit at a time. The state of
|
|
* the DATA bit can only change while the CLOCK line is held low.
|
|
* Transactions work basically like this:
|
|
*
|
|
* 1) Send the EEPROM_START sequence to prepare the EEPROM for
|
|
* accepting commands. This pulls the clock high, sets
|
|
* the data bit to 0, enables transmission to the EEPROM,
|
|
* pulls the data bit up to 1, then pulls the clock low.
|
|
* The idea is to do a 0 to 1 transition of the data bit
|
|
* while the clock pin is held high.
|
|
*
|
|
* 2) To write a bit to the EEPROM, set the TXENABLE bit, then
|
|
* set the EDATA bit to send a 1 or clear it to send a 0.
|
|
* Finally, set and then clear ECLOK. Strobing the clock
|
|
* transmits the bit. After 8 bits have been written, the
|
|
* EEPROM should respond with an ACK, which should be read.
|
|
*
|
|
* 3) To read a bit from the EEPROM, clear the TXENABLE bit,
|
|
* then set ECLOK. The bit can then be read by reading EDATA.
|
|
* ECLOCK should then be cleared again. This can be repeated
|
|
* 8 times to read a whole byte, after which the
|
|
*
|
|
* 4) We need to send the address byte to the EEPROM. For this
|
|
* we have to send the write control byte to the EEPROM to
|
|
* tell it to accept data. The byte is 0xA0. The EEPROM should
|
|
* ack this. The address byte can be send after that.
|
|
*
|
|
* 5) Now we have to tell the EEPROM to send us data. For that we
|
|
* have to transmit the read control byte, which is 0xA1. This
|
|
* byte should also be acked. We can then read the data bits
|
|
* from the EEPROM.
|
|
*
|
|
* 6) When we're all finished, send the EEPROM_STOP sequence.
|
|
*
|
|
* Note that we use the ThunderLAN's NetSio register to access the
|
|
* EEPROM, however there is an alternate method. There is a PCI NVRAM
|
|
* register at PCI offset 0xB4 which can also be used with minor changes.
|
|
* The difference is that access to PCI registers via pci_conf_read()
|
|
* and pci_conf_write() is done using programmed I/O, which we want to
|
|
* avoid.
|
|
*/
|
|
|
|
/*
|
|
* Note that EEPROM_START leaves transmission enabled.
|
|
*/
|
|
#define EEPROM_START \
|
|
tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\
|
|
tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \
|
|
tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\
|
|
tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\
|
|
tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */
|
|
|
|
/*
|
|
* EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
|
|
* that no further data can be written to the EEPROM I/O pin.
|
|
*/
|
|
#define EEPROM_STOP \
|
|
tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \
|
|
tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \
|
|
tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \
|
|
tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \
|
|
tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \
|
|
tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \
|
|
tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */
|
|
|
|
|
|
/*
|
|
* Microchip Technology 24Cxx EEPROM control bytes
|
|
*/
|
|
#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */
|
|
#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */
|
|
|
|
#ifdef __alpha__
|
|
#undef vtophys
|
|
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
|
|
#endif
|