45d426a34e
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
118 lines
4.1 KiB
C
118 lines
4.1 KiB
C
/* $OpenBSD: trap.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */
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/*-
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: trap.h 1.1 90/07/09
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* from: @(#)trap.h 8.1 (Berkeley) 6/10/93
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* JNPR: trap.h,v 1.3 2006/12/02 09:53:41 katta
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* $FreeBSD$
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*/
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#ifndef _MACHINE_TRAP_H_
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#define _MACHINE_TRAP_H_
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/*
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* Trap codes also known in trap.c for name strings.
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* Used for indexing so modify with care.
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*/
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#define T_INT 0 /* Interrupt pending */
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#define T_TLB_MOD 1 /* TLB modified fault */
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#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
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#define T_TLB_ST_MISS 3 /* TLB miss on a store */
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#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
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#define T_ADDR_ERR_ST 5 /* Address error on a store */
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#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
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#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
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#define T_SYSCALL 8 /* System call */
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#define T_BREAK 9 /* Breakpoint */
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#define T_RES_INST 10 /* Reserved instruction exception */
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#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
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#define T_OVFLOW 12 /* Arithmetic overflow */
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#define T_TRAP 13 /* Trap instruction */
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#define T_VCEI 14 /* Virtual coherency instruction */
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#define T_FPE 15 /* Floating point exception */
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#define T_IWATCH 16 /* Inst. Watch address reference */
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#define T_C2E 18 /* Exception from coprocessor 2 */
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#define T_DWATCH 23 /* Data Watch address reference */
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#define T_MCHECK 24 /* Received an MCHECK */
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#define T_VCED 31 /* Virtual coherency data */
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#define T_USER 0x20 /* user-mode flag or'ed with type */
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#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
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struct trapdebug { /* trap history buffer for debugging */
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u_int status;
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u_int cause;
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u_int vadr;
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u_int pc;
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u_int ra;
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u_int sp;
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u_int code;
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};
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#define trapdebug_enter(x, cd) { \
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intrmask_t s = disableintr(); \
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trp->status = x->sr; \
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trp->cause = x->cause; \
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trp->vadr = x->badvaddr; \
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trp->pc = x->pc; \
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trp->sp = x->sp; \
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trp->ra = x->ra; \
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trp->code = cd; \
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if (++trp == &trapdebug[TRAPSIZE]) \
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trp = trapdebug; \
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restoreintr(s); \
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}
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#define TRAPSIZE 10 /* Trap log buffer length */
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extern struct trapdebug trapdebug[TRAPSIZE], *trp;
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void trapDump(char *msg);
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#else
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#define trapdebug_enter(x, cd)
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#endif
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#ifndef LOCORE /* XXX */
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int check_address(void *);
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void platform_trap_enter(void);
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void platform_trap_exit(void);
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#endif
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#endif /* !_MACHINE_TRAP_H_ */
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