ca20f8ec29
o Replace __riscv64 with (__riscv && __riscv_xlen == 64) This is required to support new GCC 7.1 compiler. This is compatible with current GCC 6.1 compiler. RISC-V is extensible ISA and the idea here is to have built-in define per each extension, so together with __riscv we will have some subset of these as well (depending on -march string passed to compiler): __riscv_compressed __riscv_atomic __riscv_mul __riscv_div __riscv_muldiv __riscv_fdiv __riscv_fsqrt __riscv_float_abi_soft __riscv_float_abi_single __riscv_float_abi_double __riscv_cmodel_medlow __riscv_cmodel_medany __riscv_cmodel_pic __riscv_xlen Reviewed by: ngie Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D11901 |
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.. | ||
AddressSpace.hpp | ||
assembly.h | ||
CompactUnwinder.hpp | ||
config.h | ||
dwarf2.h | ||
DwarfInstructions.hpp | ||
DwarfParser.hpp | ||
EHHeaderParser.hpp | ||
libunwind_ext.h | ||
libunwind.cpp | ||
Registers.hpp | ||
Unwind_AppleExtras.cpp | ||
unwind_ext.h | ||
Unwind-EHABI.cpp | ||
Unwind-EHABI.h | ||
Unwind-sjlj.c | ||
UnwindCursor.hpp | ||
UnwindLevel1-gcc-ext.c | ||
UnwindLevel1.c | ||
UnwindRegistersRestore.S | ||
UnwindRegistersSave.S |