1134 lines
39 KiB
C++
1134 lines
39 KiB
C++
//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits an assembly printer for the current target.
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// Note that this is currently fairly skeletal, but will grow over time.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmWriterInst.h"
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#include "CodeGenInstruction.h"
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#include "CodeGenRegisters.h"
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#include "CodeGenTarget.h"
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#include "SequenceToOffsetTable.h"
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#include "Types.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <algorithm>
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <deque>
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#include <iterator>
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#include <map>
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#include <set>
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#include <string>
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#include <tuple>
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#include <utility>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "asm-writer-emitter"
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namespace {
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class AsmWriterEmitter {
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RecordKeeper &Records;
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CodeGenTarget Target;
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ArrayRef<const CodeGenInstruction *> NumberedInstructions;
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std::vector<AsmWriterInst> Instructions;
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public:
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AsmWriterEmitter(RecordKeeper &R);
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void run(raw_ostream &o);
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private:
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void EmitPrintInstruction(raw_ostream &o);
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void EmitGetRegisterName(raw_ostream &o);
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void EmitPrintAliasInstruction(raw_ostream &O);
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void FindUniqueOperandCommands(std::vector<std::string> &UOC,
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std::vector<std::vector<unsigned>> &InstIdxs,
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std::vector<unsigned> &InstOpsUsed,
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bool PassSubtarget) const;
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};
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} // end anonymous namespace
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static void PrintCases(std::vector<std::pair<std::string,
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AsmWriterOperand>> &OpsToPrint, raw_ostream &O,
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bool PassSubtarget) {
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O << " case " << OpsToPrint.back().first << ":";
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AsmWriterOperand TheOp = OpsToPrint.back().second;
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OpsToPrint.pop_back();
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// Check to see if any other operands are identical in this list, and if so,
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// emit a case label for them.
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for (unsigned i = OpsToPrint.size(); i != 0; --i)
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if (OpsToPrint[i-1].second == TheOp) {
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O << "\n case " << OpsToPrint[i-1].first << ":";
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OpsToPrint.erase(OpsToPrint.begin()+i-1);
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}
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// Finally, emit the code.
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O << "\n " << TheOp.getCode(PassSubtarget);
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O << "\n break;\n";
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}
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/// EmitInstructions - Emit the last instruction in the vector and any other
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/// instructions that are suitably similar to it.
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static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
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raw_ostream &O, bool PassSubtarget) {
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AsmWriterInst FirstInst = Insts.back();
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Insts.pop_back();
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std::vector<AsmWriterInst> SimilarInsts;
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unsigned DifferingOperand = ~0;
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for (unsigned i = Insts.size(); i != 0; --i) {
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unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
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if (DiffOp != ~1U) {
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if (DifferingOperand == ~0U) // First match!
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DifferingOperand = DiffOp;
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// If this differs in the same operand as the rest of the instructions in
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// this class, move it to the SimilarInsts list.
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if (DifferingOperand == DiffOp || DiffOp == ~0U) {
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SimilarInsts.push_back(Insts[i-1]);
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Insts.erase(Insts.begin()+i-1);
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}
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}
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}
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O << " case " << FirstInst.CGI->Namespace << "::"
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<< FirstInst.CGI->TheDef->getName() << ":\n";
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for (const AsmWriterInst &AWI : SimilarInsts)
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O << " case " << AWI.CGI->Namespace << "::"
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<< AWI.CGI->TheDef->getName() << ":\n";
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for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
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if (i != DifferingOperand) {
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// If the operand is the same for all instructions, just print it.
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O << " " << FirstInst.Operands[i].getCode(PassSubtarget);
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} else {
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// If this is the operand that varies between all of the instructions,
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// emit a switch for just this operand now.
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O << " switch (MI->getOpcode()) {\n";
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O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
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std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
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OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace.str() + "::" +
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FirstInst.CGI->TheDef->getName().str(),
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FirstInst.Operands[i]));
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for (const AsmWriterInst &AWI : SimilarInsts) {
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OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace.str()+"::" +
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AWI.CGI->TheDef->getName().str(),
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AWI.Operands[i]));
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}
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std::reverse(OpsToPrint.begin(), OpsToPrint.end());
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while (!OpsToPrint.empty())
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PrintCases(OpsToPrint, O, PassSubtarget);
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O << " }";
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}
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O << "\n";
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}
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O << " break;\n";
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}
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void AsmWriterEmitter::
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FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
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std::vector<std::vector<unsigned>> &InstIdxs,
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std::vector<unsigned> &InstOpsUsed,
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bool PassSubtarget) const {
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// This vector parallels UniqueOperandCommands, keeping track of which
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// instructions each case are used for. It is a comma separated string of
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// enums.
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std::vector<std::string> InstrsForCase;
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InstrsForCase.resize(UniqueOperandCommands.size());
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InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
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for (size_t i = 0, e = Instructions.size(); i != e; ++i) {
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const AsmWriterInst &Inst = Instructions[i];
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if (Inst.Operands.empty())
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continue; // Instruction already done.
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std::string Command = " "+Inst.Operands[0].getCode(PassSubtarget)+"\n";
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// Check to see if we already have 'Command' in UniqueOperandCommands.
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// If not, add it.
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auto I = llvm::find(UniqueOperandCommands, Command);
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if (I != UniqueOperandCommands.end()) {
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size_t idx = I - UniqueOperandCommands.begin();
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InstrsForCase[idx] += ", ";
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InstrsForCase[idx] += Inst.CGI->TheDef->getName();
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InstIdxs[idx].push_back(i);
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} else {
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UniqueOperandCommands.push_back(std::move(Command));
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InstrsForCase.push_back(Inst.CGI->TheDef->getName());
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InstIdxs.emplace_back();
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InstIdxs.back().push_back(i);
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// This command matches one operand so far.
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InstOpsUsed.push_back(1);
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}
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}
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// For each entry of UniqueOperandCommands, there is a set of instructions
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// that uses it. If the next command of all instructions in the set are
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// identical, fold it into the command.
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for (size_t CommandIdx = 0, e = UniqueOperandCommands.size();
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CommandIdx != e; ++CommandIdx) {
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const auto &Idxs = InstIdxs[CommandIdx];
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for (unsigned Op = 1; ; ++Op) {
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// Find the first instruction in the set.
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const AsmWriterInst &FirstInst = Instructions[Idxs.front()];
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// If this instruction has no more operands, we isn't anything to merge
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// into this command.
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if (FirstInst.Operands.size() == Op)
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break;
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// Otherwise, scan to see if all of the other instructions in this command
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// set share the operand.
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if (std::any_of(Idxs.begin()+1, Idxs.end(),
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[&](unsigned Idx) {
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const AsmWriterInst &OtherInst = Instructions[Idx];
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return OtherInst.Operands.size() == Op ||
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OtherInst.Operands[Op] != FirstInst.Operands[Op];
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}))
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break;
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// Okay, everything in this command set has the same next operand. Add it
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// to UniqueOperandCommands and remember that it was consumed.
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std::string Command = " " +
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FirstInst.Operands[Op].getCode(PassSubtarget) + "\n";
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UniqueOperandCommands[CommandIdx] += Command;
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InstOpsUsed[CommandIdx]++;
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}
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}
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// Prepend some of the instructions each case is used for onto the case val.
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for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
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std::string Instrs = InstrsForCase[i];
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if (Instrs.size() > 70) {
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Instrs.erase(Instrs.begin()+70, Instrs.end());
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Instrs += "...";
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}
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if (!Instrs.empty())
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UniqueOperandCommands[i] = " // " + Instrs + "\n" +
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UniqueOperandCommands[i];
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}
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}
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static void UnescapeString(std::string &Str) {
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for (unsigned i = 0; i != Str.size(); ++i) {
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if (Str[i] == '\\' && i != Str.size()-1) {
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switch (Str[i+1]) {
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default: continue; // Don't execute the code after the switch.
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case 'a': Str[i] = '\a'; break;
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case 'b': Str[i] = '\b'; break;
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case 'e': Str[i] = 27; break;
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case 'f': Str[i] = '\f'; break;
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case 'n': Str[i] = '\n'; break;
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case 'r': Str[i] = '\r'; break;
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case 't': Str[i] = '\t'; break;
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case 'v': Str[i] = '\v'; break;
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case '"': Str[i] = '\"'; break;
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case '\'': Str[i] = '\''; break;
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case '\\': Str[i] = '\\'; break;
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}
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// Nuke the second character.
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Str.erase(Str.begin()+i+1);
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}
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}
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}
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/// EmitPrintInstruction - Generate the code for the "printInstruction" method
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/// implementation. Destroys all instances of AsmWriterInst information, by
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/// clearing the Instructions vector.
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void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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Record *AsmWriter = Target.getAsmWriter();
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StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
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O <<
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"/// printInstruction - This method is automatically generated by tablegen\n"
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"/// from the instruction set description.\n"
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"void " << Target.getName() << ClassName
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<< "::printInstruction(const MCInst *MI, "
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<< (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
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<< "raw_ostream &O) {\n";
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// Build an aggregate string, and build a table of offsets into it.
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SequenceToOffsetTable<std::string> StringTable;
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/// OpcodeInfo - This encodes the index of the string to use for the first
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/// chunk of the output as well as indices used for operand printing.
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std::vector<uint64_t> OpcodeInfo(NumberedInstructions.size());
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const unsigned OpcodeInfoBits = 64;
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// Add all strings to the string table upfront so it can generate an optimized
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// representation.
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for (AsmWriterInst &AWI : Instructions) {
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if (AWI.Operands[0].OperandType ==
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AsmWriterOperand::isLiteralTextOperand &&
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!AWI.Operands[0].Str.empty()) {
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std::string Str = AWI.Operands[0].Str;
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UnescapeString(Str);
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StringTable.add(Str);
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}
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}
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StringTable.layout();
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unsigned MaxStringIdx = 0;
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for (AsmWriterInst &AWI : Instructions) {
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unsigned Idx;
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if (AWI.Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand ||
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AWI.Operands[0].Str.empty()) {
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// Something handled by the asmwriter printer, but with no leading string.
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Idx = StringTable.get("");
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} else {
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std::string Str = AWI.Operands[0].Str;
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UnescapeString(Str);
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Idx = StringTable.get(Str);
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MaxStringIdx = std::max(MaxStringIdx, Idx);
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// Nuke the string from the operand list. It is now handled!
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AWI.Operands.erase(AWI.Operands.begin());
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}
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// Bias offset by one since we want 0 as a sentinel.
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OpcodeInfo[AWI.CGIIndex] = Idx+1;
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}
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// Figure out how many bits we used for the string index.
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unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2);
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// To reduce code size, we compactify common instructions into a few bits
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// in the opcode-indexed table.
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unsigned BitsLeft = OpcodeInfoBits-AsmStrBits;
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std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
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while (true) {
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std::vector<std::string> UniqueOperandCommands;
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std::vector<std::vector<unsigned>> InstIdxs;
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std::vector<unsigned> NumInstOpsHandled;
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FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
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NumInstOpsHandled, PassSubtarget);
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// If we ran out of operands to print, we're done.
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if (UniqueOperandCommands.empty()) break;
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// Compute the number of bits we need to represent these cases, this is
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// ceil(log2(numentries)).
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unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
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// If we don't have enough bits for this operand, don't include it.
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if (NumBits > BitsLeft) {
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DEBUG(errs() << "Not enough bits to densely encode " << NumBits
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<< " more bits\n");
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break;
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}
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// Otherwise, we can include this in the initial lookup table. Add it in.
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for (size_t i = 0, e = InstIdxs.size(); i != e; ++i) {
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unsigned NumOps = NumInstOpsHandled[i];
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for (unsigned Idx : InstIdxs[i]) {
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OpcodeInfo[Instructions[Idx].CGIIndex] |=
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(uint64_t)i << (OpcodeInfoBits-BitsLeft);
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// Remove the info about this operand from the instruction.
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AsmWriterInst &Inst = Instructions[Idx];
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if (!Inst.Operands.empty()) {
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assert(NumOps <= Inst.Operands.size() &&
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"Can't remove this many ops!");
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Inst.Operands.erase(Inst.Operands.begin(),
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Inst.Operands.begin()+NumOps);
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}
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}
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}
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BitsLeft -= NumBits;
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// Remember the handlers for this set of operands.
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TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands));
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}
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// Emit the string table itself.
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O << " static const char AsmStrs[] = {\n";
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StringTable.emit(O, printChar);
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O << " };\n\n";
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// Emit the lookup tables in pieces to minimize wasted bytes.
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unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8;
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unsigned Table = 0, Shift = 0;
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SmallString<128> BitsString;
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raw_svector_ostream BitsOS(BitsString);
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// If the total bits is more than 32-bits we need to use a 64-bit type.
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BitsOS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32)
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<< "_t Bits = 0;\n";
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while (BytesNeeded != 0) {
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// Figure out how big this table section needs to be, but no bigger than 4.
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unsigned TableSize = std::min(1 << Log2_32(BytesNeeded), 4);
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BytesNeeded -= TableSize;
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TableSize *= 8; // Convert to bits;
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uint64_t Mask = (1ULL << TableSize) - 1;
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O << " static const uint" << TableSize << "_t OpInfo" << Table
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<< "[] = {\n";
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// "
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<< NumberedInstructions[i]->TheDef->getName() << "\n";
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}
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O << " };\n\n";
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// Emit string to combine the individual table lookups.
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BitsOS << " Bits |= ";
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// If the total bits is more than 32-bits we need to use a 64-bit type.
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if (BitsLeft < (OpcodeInfoBits - 32))
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BitsOS << "(uint64_t)";
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BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n";
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// Prepare the shift for the next iteration and increment the table count.
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Shift += TableSize;
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++Table;
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}
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// Emit the initial tab character.
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O << " O << \"\\t\";\n\n";
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O << " // Emit the opcode for the instruction.\n";
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O << BitsString;
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// Emit the starting string.
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O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
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<< " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
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// Output the table driven operand information.
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BitsLeft = OpcodeInfoBits-AsmStrBits;
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for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
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std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
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// Compute the number of bits we need to represent these cases, this is
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// ceil(log2(numentries)).
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unsigned NumBits = Log2_32_Ceil(Commands.size());
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assert(NumBits <= BitsLeft && "consistency error");
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// Emit code to extract this field from Bits.
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O << "\n // Fragment " << i << " encoded into " << NumBits
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<< " bits for " << Commands.size() << " unique commands.\n";
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if (Commands.size() == 2) {
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// Emit two possibilitys with if/else.
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O << " if ((Bits >> "
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<< (OpcodeInfoBits-BitsLeft) << ") & "
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<< ((1 << NumBits)-1) << ") {\n"
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<< Commands[1]
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<< " } else {\n"
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<< Commands[0]
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<< " }\n\n";
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} else if (Commands.size() == 1) {
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// Emit a single possibility.
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O << Commands[0] << "\n\n";
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} else {
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O << " switch ((Bits >> "
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<< (OpcodeInfoBits-BitsLeft) << ") & "
|
|
<< ((1 << NumBits)-1) << ") {\n"
|
|
<< " default: llvm_unreachable(\"Invalid command number.\");\n";
|
|
|
|
// Print out all the cases.
|
|
for (unsigned j = 0, e = Commands.size(); j != e; ++j) {
|
|
O << " case " << j << ":\n";
|
|
O << Commands[j];
|
|
O << " break;\n";
|
|
}
|
|
O << " }\n\n";
|
|
}
|
|
BitsLeft -= NumBits;
|
|
}
|
|
|
|
// Okay, delete instructions with no operand info left.
|
|
auto I = llvm::remove_if(Instructions,
|
|
[](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
|
|
Instructions.erase(I, Instructions.end());
|
|
|
|
|
|
// Because this is a vector, we want to emit from the end. Reverse all of the
|
|
// elements in the vector.
|
|
std::reverse(Instructions.begin(), Instructions.end());
|
|
|
|
|
|
// Now that we've emitted all of the operand info that fit into 64 bits, emit
|
|
// information for those instructions that are left. This is a less dense
|
|
// encoding, but we expect the main 64-bit table to handle the majority of
|
|
// instructions.
|
|
if (!Instructions.empty()) {
|
|
// Find the opcode # of inline asm.
|
|
O << " switch (MI->getOpcode()) {\n";
|
|
O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
|
|
while (!Instructions.empty())
|
|
EmitInstructions(Instructions, O, PassSubtarget);
|
|
|
|
O << " }\n";
|
|
}
|
|
|
|
O << "}\n";
|
|
}
|
|
|
|
static void
|
|
emitRegisterNameString(raw_ostream &O, StringRef AltName,
|
|
const std::deque<CodeGenRegister> &Registers) {
|
|
SequenceToOffsetTable<std::string> StringTable;
|
|
SmallVector<std::string, 4> AsmNames(Registers.size());
|
|
unsigned i = 0;
|
|
for (const auto &Reg : Registers) {
|
|
std::string &AsmName = AsmNames[i++];
|
|
|
|
// "NoRegAltName" is special. We don't need to do a lookup for that,
|
|
// as it's just a reference to the default register name.
|
|
if (AltName == "" || AltName == "NoRegAltName") {
|
|
AsmName = Reg.TheDef->getValueAsString("AsmName");
|
|
if (AsmName.empty())
|
|
AsmName = Reg.getName();
|
|
} else {
|
|
// Make sure the register has an alternate name for this index.
|
|
std::vector<Record*> AltNameList =
|
|
Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
|
|
unsigned Idx = 0, e;
|
|
for (e = AltNameList.size();
|
|
Idx < e && (AltNameList[Idx]->getName() != AltName);
|
|
++Idx)
|
|
;
|
|
// If the register has an alternate name for this index, use it.
|
|
// Otherwise, leave it empty as an error flag.
|
|
if (Idx < e) {
|
|
std::vector<StringRef> AltNames =
|
|
Reg.TheDef->getValueAsListOfStrings("AltNames");
|
|
if (AltNames.size() <= Idx)
|
|
PrintFatalError(Reg.TheDef->getLoc(),
|
|
"Register definition missing alt name for '" +
|
|
AltName + "'.");
|
|
AsmName = AltNames[Idx];
|
|
}
|
|
}
|
|
StringTable.add(AsmName);
|
|
}
|
|
|
|
StringTable.layout();
|
|
O << " static const char AsmStrs" << AltName << "[] = {\n";
|
|
StringTable.emit(O, printChar);
|
|
O << " };\n\n";
|
|
|
|
O << " static const " << getMinimalTypeForRange(StringTable.size() - 1, 32)
|
|
<< " RegAsmOffset" << AltName << "[] = {";
|
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
|
if ((i % 14) == 0)
|
|
O << "\n ";
|
|
O << StringTable.get(AsmNames[i]) << ", ";
|
|
}
|
|
O << "\n };\n"
|
|
<< "\n";
|
|
}
|
|
|
|
void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
const auto &Registers = Target.getRegBank().getRegisters();
|
|
const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices();
|
|
bool hasAltNames = AltNameIndices.size() > 1;
|
|
StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
|
|
|
|
O <<
|
|
"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
|
|
"/// from the register set description. This returns the assembler name\n"
|
|
"/// for the specified register.\n"
|
|
"const char *" << Target.getName() << ClassName << "::";
|
|
if (hasAltNames)
|
|
O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
|
|
else
|
|
O << "getRegisterName(unsigned RegNo) {\n";
|
|
O << " assert(RegNo && RegNo < " << (Registers.size()+1)
|
|
<< " && \"Invalid register number!\");\n"
|
|
<< "\n";
|
|
|
|
if (hasAltNames) {
|
|
for (const Record *R : AltNameIndices)
|
|
emitRegisterNameString(O, R->getName(), Registers);
|
|
} else
|
|
emitRegisterNameString(O, "", Registers);
|
|
|
|
if (hasAltNames) {
|
|
O << " switch(AltIdx) {\n"
|
|
<< " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
|
|
for (const Record *R : AltNameIndices) {
|
|
StringRef AltName = R->getName();
|
|
O << " case ";
|
|
if (!Namespace.empty())
|
|
O << Namespace << "::";
|
|
O << AltName << ":\n"
|
|
<< " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName
|
|
<< "[RegNo-1]) &&\n"
|
|
<< " \"Invalid alt name index for register!\");\n"
|
|
<< " return AsmStrs" << AltName << "+RegAsmOffset" << AltName
|
|
<< "[RegNo-1];\n";
|
|
}
|
|
O << " }\n";
|
|
} else {
|
|
O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
|
|
<< " \"Invalid alt name index for register!\");\n"
|
|
<< " return AsmStrs+RegAsmOffset[RegNo-1];\n";
|
|
}
|
|
O << "}\n";
|
|
}
|
|
|
|
namespace {
|
|
|
|
// IAPrinter - Holds information about an InstAlias. Two InstAliases match if
|
|
// they both have the same conditionals. In which case, we cannot print out the
|
|
// alias for that pattern.
|
|
class IAPrinter {
|
|
std::vector<std::string> Conds;
|
|
std::map<StringRef, std::pair<int, int>> OpMap;
|
|
|
|
std::string Result;
|
|
std::string AsmString;
|
|
|
|
public:
|
|
IAPrinter(std::string R, std::string AS)
|
|
: Result(std::move(R)), AsmString(std::move(AS)) {}
|
|
|
|
void addCond(const std::string &C) { Conds.push_back(C); }
|
|
|
|
void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
|
|
assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
|
|
assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF &&
|
|
"Idx out of range");
|
|
OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
|
|
}
|
|
|
|
bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
|
|
int getOpIndex(StringRef Op) { return OpMap[Op].first; }
|
|
std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
|
|
|
|
std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start,
|
|
StringRef::iterator End) {
|
|
StringRef::iterator I = Start;
|
|
StringRef::iterator Next;
|
|
if (*I == '{') {
|
|
// ${some_name}
|
|
Start = ++I;
|
|
while (I != End && *I != '}')
|
|
++I;
|
|
Next = I;
|
|
// eat the final '}'
|
|
if (Next != End)
|
|
++Next;
|
|
} else {
|
|
// $name, just eat the usual suspects.
|
|
while (I != End &&
|
|
((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') ||
|
|
(*I >= '0' && *I <= '9') || *I == '_'))
|
|
++I;
|
|
Next = I;
|
|
}
|
|
|
|
return std::make_pair(StringRef(Start, I - Start), Next);
|
|
}
|
|
|
|
void print(raw_ostream &O) {
|
|
if (Conds.empty()) {
|
|
O.indent(6) << "return true;\n";
|
|
return;
|
|
}
|
|
|
|
O << "if (";
|
|
|
|
for (std::vector<std::string>::iterator
|
|
I = Conds.begin(), E = Conds.end(); I != E; ++I) {
|
|
if (I != Conds.begin()) {
|
|
O << " &&\n";
|
|
O.indent(8);
|
|
}
|
|
|
|
O << *I;
|
|
}
|
|
|
|
O << ") {\n";
|
|
O.indent(6) << "// " << Result << "\n";
|
|
|
|
// Directly mangle mapped operands into the string. Each operand is
|
|
// identified by a '$' sign followed by a byte identifying the number of the
|
|
// operand. We add one to the index to avoid zero bytes.
|
|
StringRef ASM(AsmString);
|
|
SmallString<128> OutString;
|
|
raw_svector_ostream OS(OutString);
|
|
for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) {
|
|
OS << *I;
|
|
if (*I == '$') {
|
|
StringRef Name;
|
|
std::tie(Name, I) = parseName(++I, E);
|
|
assert(isOpMapped(Name) && "Unmapped operand!");
|
|
|
|
int OpIndex, PrintIndex;
|
|
std::tie(OpIndex, PrintIndex) = getOpData(Name);
|
|
if (PrintIndex == -1) {
|
|
// Can use the default printOperand route.
|
|
OS << format("\\x%02X", (unsigned char)OpIndex + 1);
|
|
} else
|
|
// 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
|
|
// number, and which of our pre-detected Methods to call.
|
|
OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
|
|
} else {
|
|
++I;
|
|
}
|
|
}
|
|
|
|
// Emit the string.
|
|
O.indent(6) << "AsmString = \"" << OutString << "\";\n";
|
|
|
|
O.indent(6) << "break;\n";
|
|
O.indent(4) << '}';
|
|
}
|
|
|
|
bool operator==(const IAPrinter &RHS) const {
|
|
if (Conds.size() != RHS.Conds.size())
|
|
return false;
|
|
|
|
unsigned Idx = 0;
|
|
for (const auto &str : Conds)
|
|
if (str != RHS.Conds[Idx++])
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
|
|
std::string FlatAsmString =
|
|
CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);
|
|
AsmString = FlatAsmString;
|
|
|
|
return AsmString.count(' ') + AsmString.count('\t');
|
|
}
|
|
|
|
namespace {
|
|
|
|
struct AliasPriorityComparator {
|
|
typedef std::pair<CodeGenInstAlias, int> ValueType;
|
|
bool operator()(const ValueType &LHS, const ValueType &RHS) const {
|
|
if (LHS.second == RHS.second) {
|
|
// We don't actually care about the order, but for consistency it
|
|
// shouldn't depend on pointer comparisons.
|
|
return LessRecordByID()(LHS.first.TheDef, RHS.first.TheDef);
|
|
}
|
|
|
|
// Aliases with larger priorities should be considered first.
|
|
return LHS.second > RHS.second;
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
|
|
O << "\n#ifdef PRINT_ALIAS_INSTR\n";
|
|
O << "#undef PRINT_ALIAS_INSTR\n\n";
|
|
|
|
//////////////////////////////
|
|
// Gather information about aliases we need to print
|
|
//////////////////////////////
|
|
|
|
// Emit the method that prints the alias instruction.
|
|
StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
|
|
unsigned Variant = AsmWriter->getValueAsInt("Variant");
|
|
bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
|
|
|
|
std::vector<Record*> AllInstAliases =
|
|
Records.getAllDerivedDefinitions("InstAlias");
|
|
|
|
// Create a map from the qualified name to a list of potential matches.
|
|
typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
|
|
AliasWithPriority;
|
|
std::map<std::string, AliasWithPriority> AliasMap;
|
|
for (Record *R : AllInstAliases) {
|
|
int Priority = R->getValueAsInt("EmitPriority");
|
|
if (Priority < 1)
|
|
continue; // Aliases with priority 0 are never emitted.
|
|
|
|
const DagInit *DI = R->getValueAsDag("ResultInst");
|
|
const DefInit *Op = cast<DefInit>(DI->getOperator());
|
|
AliasMap[getQualifiedName(Op->getDef())].insert(
|
|
std::make_pair(CodeGenInstAlias(R, Variant, Target), Priority));
|
|
}
|
|
|
|
// A map of which conditions need to be met for each instruction operand
|
|
// before it can be matched to the mnemonic.
|
|
std::map<std::string, std::vector<IAPrinter>> IAPrinterMap;
|
|
|
|
std::vector<std::string> PrintMethods;
|
|
|
|
// A list of MCOperandPredicates for all operands in use, and the reverse map
|
|
std::vector<const Record*> MCOpPredicates;
|
|
DenseMap<const Record*, unsigned> MCOpPredicateMap;
|
|
|
|
for (auto &Aliases : AliasMap) {
|
|
for (auto &Alias : Aliases.second) {
|
|
const CodeGenInstAlias &CGA = Alias.first;
|
|
unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
|
|
unsigned NumResultOps =
|
|
CountNumOperands(CGA.ResultInst->AsmString, Variant);
|
|
|
|
// Don't emit the alias if it has more operands than what it's aliasing.
|
|
if (NumResultOps < CountNumOperands(CGA.AsmString, Variant))
|
|
continue;
|
|
|
|
IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString);
|
|
|
|
StringRef Namespace = Target.getName();
|
|
std::vector<Record *> ReqFeatures;
|
|
if (PassSubtarget) {
|
|
// We only consider ReqFeatures predicates if PassSubtarget
|
|
std::vector<Record *> RF =
|
|
CGA.TheDef->getValueAsListOfDefs("Predicates");
|
|
copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
|
|
return R->getValueAsBit("AssemblerMatcherPredicate");
|
|
});
|
|
}
|
|
|
|
unsigned NumMIOps = 0;
|
|
for (auto &Operand : CGA.ResultOperands)
|
|
NumMIOps += Operand.getMINumOperands();
|
|
|
|
std::string Cond;
|
|
Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps);
|
|
IAP.addCond(Cond);
|
|
|
|
bool CantHandle = false;
|
|
|
|
unsigned MIOpNum = 0;
|
|
for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
|
|
std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")";
|
|
|
|
const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
|
|
|
|
switch (RO.Kind) {
|
|
case CodeGenInstAlias::ResultOperand::K_Record: {
|
|
const Record *Rec = RO.getRecord();
|
|
StringRef ROName = RO.getName();
|
|
int PrintMethodIdx = -1;
|
|
|
|
// These two may have a PrintMethod, which we want to record (if it's
|
|
// the first time we've seen it) and provide an index for the aliasing
|
|
// code to use.
|
|
if (Rec->isSubClassOf("RegisterOperand") ||
|
|
Rec->isSubClassOf("Operand")) {
|
|
StringRef PrintMethod = Rec->getValueAsString("PrintMethod");
|
|
if (PrintMethod != "" && PrintMethod != "printOperand") {
|
|
PrintMethodIdx =
|
|
llvm::find(PrintMethods, PrintMethod) - PrintMethods.begin();
|
|
if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
|
|
PrintMethods.push_back(PrintMethod);
|
|
}
|
|
}
|
|
|
|
if (Rec->isSubClassOf("RegisterOperand"))
|
|
Rec = Rec->getValueAsDef("RegClass");
|
|
if (Rec->isSubClassOf("RegisterClass")) {
|
|
IAP.addCond(Op + ".isReg()");
|
|
|
|
if (!IAP.isOpMapped(ROName)) {
|
|
IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
|
|
Record *R = CGA.ResultOperands[i].getRecord();
|
|
if (R->isSubClassOf("RegisterOperand"))
|
|
R = R->getValueAsDef("RegClass");
|
|
Cond = std::string("MRI.getRegClass(") + Target.getName().str() +
|
|
"::" + R->getName().str() + "RegClassID).contains(" + Op +
|
|
".getReg())";
|
|
} else {
|
|
Cond = Op + ".getReg() == MI->getOperand(" +
|
|
utostr(IAP.getOpIndex(ROName)) + ").getReg()";
|
|
}
|
|
} else {
|
|
// Assume all printable operands are desired for now. This can be
|
|
// overridden in the InstAlias instantiation if necessary.
|
|
IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
|
|
|
|
// There might be an additional predicate on the MCOperand
|
|
unsigned Entry = MCOpPredicateMap[Rec];
|
|
if (!Entry) {
|
|
if (!Rec->isValueUnset("MCOperandPredicate")) {
|
|
MCOpPredicates.push_back(Rec);
|
|
Entry = MCOpPredicates.size();
|
|
MCOpPredicateMap[Rec] = Entry;
|
|
} else
|
|
break; // No conditions on this operand at all
|
|
}
|
|
Cond = (Target.getName() + ClassName + "ValidateMCOperand(" + Op +
|
|
", STI, " + utostr(Entry) + ")")
|
|
.str();
|
|
}
|
|
// for all subcases of ResultOperand::K_Record:
|
|
IAP.addCond(Cond);
|
|
break;
|
|
}
|
|
case CodeGenInstAlias::ResultOperand::K_Imm: {
|
|
// Just because the alias has an immediate result, doesn't mean the
|
|
// MCInst will. An MCExpr could be present, for example.
|
|
IAP.addCond(Op + ".isImm()");
|
|
|
|
Cond = Op + ".getImm() == " + itostr(CGA.ResultOperands[i].getImm());
|
|
IAP.addCond(Cond);
|
|
break;
|
|
}
|
|
case CodeGenInstAlias::ResultOperand::K_Reg:
|
|
// If this is zero_reg, something's playing tricks we're not
|
|
// equipped to handle.
|
|
if (!CGA.ResultOperands[i].getRegister()) {
|
|
CantHandle = true;
|
|
break;
|
|
}
|
|
|
|
Cond = Op + ".getReg() == " + Target.getName().str() + "::" +
|
|
CGA.ResultOperands[i].getRegister()->getName().str();
|
|
IAP.addCond(Cond);
|
|
break;
|
|
}
|
|
|
|
MIOpNum += RO.getMINumOperands();
|
|
}
|
|
|
|
if (CantHandle) continue;
|
|
|
|
for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) {
|
|
Record *R = *I;
|
|
StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
|
|
|
|
// AsmCondString has syntax [!]F(,[!]F)*
|
|
SmallVector<StringRef, 4> Ops;
|
|
SplitString(AsmCondString, Ops, ",");
|
|
assert(!Ops.empty() && "AssemblerCondString cannot be empty");
|
|
|
|
for (auto &Op : Ops) {
|
|
assert(!Op.empty() && "Empty operator");
|
|
if (Op[0] == '!')
|
|
Cond = ("!STI.getFeatureBits()[" + Namespace + "::" + Op.substr(1) +
|
|
"]")
|
|
.str();
|
|
else
|
|
Cond =
|
|
("STI.getFeatureBits()[" + Namespace + "::" + Op + "]").str();
|
|
IAP.addCond(Cond);
|
|
}
|
|
}
|
|
|
|
IAPrinterMap[Aliases.first].push_back(std::move(IAP));
|
|
}
|
|
}
|
|
|
|
//////////////////////////////
|
|
// Write out the printAliasInstr function
|
|
//////////////////////////////
|
|
|
|
std::string Header;
|
|
raw_string_ostream HeaderO(Header);
|
|
|
|
HeaderO << "bool " << Target.getName() << ClassName
|
|
<< "::printAliasInstr(const MCInst"
|
|
<< " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
|
|
<< "raw_ostream &OS) {\n";
|
|
|
|
std::string Cases;
|
|
raw_string_ostream CasesO(Cases);
|
|
|
|
for (auto &Entry : IAPrinterMap) {
|
|
std::vector<IAPrinter> &IAPs = Entry.second;
|
|
std::vector<IAPrinter*> UniqueIAPs;
|
|
|
|
for (auto &LHS : IAPs) {
|
|
bool IsDup = false;
|
|
for (const auto &RHS : IAPs) {
|
|
if (&LHS != &RHS && LHS == RHS) {
|
|
IsDup = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!IsDup)
|
|
UniqueIAPs.push_back(&LHS);
|
|
}
|
|
|
|
if (UniqueIAPs.empty()) continue;
|
|
|
|
CasesO.indent(2) << "case " << Entry.first << ":\n";
|
|
|
|
for (IAPrinter *IAP : UniqueIAPs) {
|
|
CasesO.indent(4);
|
|
IAP->print(CasesO);
|
|
CasesO << '\n';
|
|
}
|
|
|
|
CasesO.indent(4) << "return false;\n";
|
|
}
|
|
|
|
if (CasesO.str().empty()) {
|
|
O << HeaderO.str();
|
|
O << " return false;\n";
|
|
O << "}\n\n";
|
|
O << "#endif // PRINT_ALIAS_INSTR\n";
|
|
return;
|
|
}
|
|
|
|
if (!MCOpPredicates.empty())
|
|
O << "static bool " << Target.getName() << ClassName
|
|
<< "ValidateMCOperand(const MCOperand &MCOp,\n"
|
|
<< " const MCSubtargetInfo &STI,\n"
|
|
<< " unsigned PredicateIndex);\n";
|
|
|
|
O << HeaderO.str();
|
|
O.indent(2) << "const char *AsmString;\n";
|
|
O.indent(2) << "switch (MI->getOpcode()) {\n";
|
|
O.indent(2) << "default: return false;\n";
|
|
O << CasesO.str();
|
|
O.indent(2) << "}\n\n";
|
|
|
|
// Code that prints the alias, replacing the operands with the ones from the
|
|
// MCInst.
|
|
O << " unsigned I = 0;\n";
|
|
O << " while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&\n";
|
|
O << " AsmString[I] != '$' && AsmString[I] != '\\0')\n";
|
|
O << " ++I;\n";
|
|
O << " OS << '\\t' << StringRef(AsmString, I);\n";
|
|
|
|
O << " if (AsmString[I] != '\\0') {\n";
|
|
O << " if (AsmString[I] == ' ' || AsmString[I] == '\\t')";
|
|
O << " OS << '\\t';\n";
|
|
O << " do {\n";
|
|
O << " if (AsmString[I] == '$') {\n";
|
|
O << " ++I;\n";
|
|
O << " if (AsmString[I] == (char)0xff) {\n";
|
|
O << " ++I;\n";
|
|
O << " int OpIdx = AsmString[I++] - 1;\n";
|
|
O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
|
|
O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, ";
|
|
O << (PassSubtarget ? "STI, " : "");
|
|
O << "OS);\n";
|
|
O << " } else\n";
|
|
O << " printOperand(MI, unsigned(AsmString[I++]) - 1, ";
|
|
O << (PassSubtarget ? "STI, " : "");
|
|
O << "OS);\n";
|
|
O << " } else {\n";
|
|
O << " OS << AsmString[I++];\n";
|
|
O << " }\n";
|
|
O << " } while (AsmString[I] != '\\0');\n";
|
|
O << " }\n\n";
|
|
|
|
O << " return true;\n";
|
|
O << "}\n\n";
|
|
|
|
//////////////////////////////
|
|
// Write out the printCustomAliasOperand function
|
|
//////////////////////////////
|
|
|
|
O << "void " << Target.getName() << ClassName << "::"
|
|
<< "printCustomAliasOperand(\n"
|
|
<< " const MCInst *MI, unsigned OpIdx,\n"
|
|
<< " unsigned PrintMethodIdx,\n"
|
|
<< (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "")
|
|
<< " raw_ostream &OS) {\n";
|
|
if (PrintMethods.empty())
|
|
O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n";
|
|
else {
|
|
O << " switch (PrintMethodIdx) {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
|
|
<< " break;\n";
|
|
|
|
for (unsigned i = 0; i < PrintMethods.size(); ++i) {
|
|
O << " case " << i << ":\n"
|
|
<< " " << PrintMethods[i] << "(MI, OpIdx, "
|
|
<< (PassSubtarget ? "STI, " : "") << "OS);\n"
|
|
<< " break;\n";
|
|
}
|
|
O << " }\n";
|
|
}
|
|
O << "}\n\n";
|
|
|
|
if (!MCOpPredicates.empty()) {
|
|
O << "static bool " << Target.getName() << ClassName
|
|
<< "ValidateMCOperand(const MCOperand &MCOp,\n"
|
|
<< " const MCSubtargetInfo &STI,\n"
|
|
<< " unsigned PredicateIndex) {\n"
|
|
<< " switch (PredicateIndex) {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
|
|
<< " break;\n";
|
|
|
|
for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
|
|
Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate");
|
|
if (CodeInit *SI = dyn_cast<CodeInit>(MCOpPred)) {
|
|
O << " case " << i + 1 << ": {\n"
|
|
<< SI->getValue() << "\n"
|
|
<< " }\n";
|
|
} else
|
|
llvm_unreachable("Unexpected MCOperandPredicate field!");
|
|
}
|
|
O << " }\n"
|
|
<< "}\n\n";
|
|
}
|
|
|
|
O << "#endif // PRINT_ALIAS_INSTR\n";
|
|
}
|
|
|
|
AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
|
|
Record *AsmWriter = Target.getAsmWriter();
|
|
unsigned Variant = AsmWriter->getValueAsInt("Variant");
|
|
|
|
// Get the instruction numbering.
|
|
NumberedInstructions = Target.getInstructionsByEnumValue();
|
|
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
const CodeGenInstruction *I = NumberedInstructions[i];
|
|
if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
|
|
Instructions.emplace_back(*I, i, Variant);
|
|
}
|
|
}
|
|
|
|
void AsmWriterEmitter::run(raw_ostream &O) {
|
|
EmitPrintInstruction(O);
|
|
EmitGetRegisterName(O);
|
|
EmitPrintAliasInstruction(O);
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
|
|
emitSourceFileHeader("Assembly Writer Source Fragment", OS);
|
|
AsmWriterEmitter(RK).run(OS);
|
|
}
|
|
|
|
} // end namespace llvm
|