718cf2ccb9
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186 lines
6.8 KiB
C
186 lines
6.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2015-2016 Hiroki Mori.
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* Copyright (c) 2011-2012 Stefan Bethke.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_ETHERSWITCH_RTL8366RBVAR_H_
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#define _DEV_ETHERSWITCH_RTL8366RBVAR_H_
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#define RTL8366RB 0
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#define RTL8366SR 1
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#define RTL8366_IIC_ADDR 0xa8
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#define RTL_IICBUS_TIMEOUT 100 /* us */
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#define RTL_IICBUS_READ 1
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#define RTL_IICBUS_WRITE 0
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/* number of times to try and select the chip on the I2C bus */
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#define RTL_IICBUS_RETRIES 3
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#define RTL_IICBUS_RETRY_SLEEP (hz/1000)
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/* Register definitions */
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/* Switch Global Configuration */
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#define RTL8366_SGCR 0x0000
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#define RTL8366_SGCR_EN_BC_STORM_CTRL 0x0001
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#define RTL8366_SGCR_MAX_LENGTH_MASK 0x0030
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#define RTL8366_SGCR_MAX_LENGTH_1522 0x0000
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#define RTL8366_SGCR_MAX_LENGTH_1536 0x0010
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#define RTL8366_SGCR_MAX_LENGTH_1552 0x0020
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#define RTL8366_SGCR_MAX_LENGTH_9216 0x0030
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#define RTL8366_SGCR_EN_VLAN 0x2000
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#define RTL8366_SGCR_EN_VLAN_4KTB 0x4000
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#define RTL8366_SGCR_EN_QOS 0x8000
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/* Port Enable Control: DISABLE_PORT[5:0] */
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#define RTL8366_PECR 0x0001
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/* Switch Security Control 0: DIS_LEARN[5:0] */
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#define RTL8366_SSCR0 0x0002
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/* Switch Security Control 1: DIS_AGE[5:0] */
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#define RTL8366_SSCR1 0x0003
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/* Switch Security Control 2 */
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#define RTL8366_SSCR2 0x0004
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#define RTL8366_SSCR2_DROP_UNKNOWN_DA 0x0001
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/* Port Link Status: two ports per register */
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#define RTL8366_PLSR_BASE (sc->chip_type == 0 ? 0x0014 : 0x0060)
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#define RTL8366_PLSR_SPEED_MASK 0x03
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#define RTL8366_PLSR_SPEED_10 0x00
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#define RTL8366_PLSR_SPEED_100 0x01
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#define RTL8366_PLSR_SPEED_1000 0x02
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#define RTL8366_PLSR_FULLDUPLEX 0x04
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#define RTL8366_PLSR_LINK 0x10
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#define RTL8366_PLSR_TXPAUSE 0x20
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#define RTL8366_PLSR_RXPAUSE 0x40
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#define RTL8366_PLSR_NO_AUTO 0x80
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/* VLAN Member Configuration, 3 or 2 registers per VLAN */
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#define RTL8366_VMCR_BASE (sc->chip_type == 0 ? 0x0020 : 0x0016)
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#define RTL8366_VMCR_MULT (sc->chip_type == 0 ? 3 : 2)
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#define RTL8366_VMCR_DOT1Q_REG 0
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#define RTL8366_VMCR_DOT1Q_VID_SHIFT 0
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#define RTL8366_VMCR_DOT1Q_VID_MASK 0x0fff
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#define RTL8366_VMCR_DOT1Q_PCP_SHIFT 12
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#define RTL8366_VMCR_DOT1Q_PCP_MASK 0x7000
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#define RTL8366_VMCR_MU_REG 1
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#define RTL8366_VMCR_MU_MEMBER_SHIFT 0
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#define RTL8366_VMCR_MU_MEMBER_MASK (sc->chip_type == 0 ? 0x00ff : 0x003f)
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#define RTL8366_VMCR_MU_UNTAG_SHIFT (sc->chip_type == 0 ? 8 : 6)
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#define RTL8366_VMCR_MU_UNTAG_MASK (sc->chip_type == 0 ? 0xff00 : 0x0fc0)
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#define RTL8366_VMCR_FID_REG (sc->chip_type == 0 ? 2 : 1)
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#define RTL8366_VMCR_FID_FID_SHIFT (sc->chip_type == 0 ? 0 : 12)
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#define RTL8366_VMCR_FID_FID_MASK (sc->chip_type == 0 ? 0x0007 : 0x7000)
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#define RTL8366_VMCR(_reg, _vlan) \
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(RTL8366_VMCR_BASE + _reg + _vlan * RTL8366_VMCR_MULT)
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/* VLAN Identifier */
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#define RTL8366_VMCR_VID(_r) \
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(_r[RTL8366_VMCR_DOT1Q_REG] & RTL8366_VMCR_DOT1Q_VID_MASK)
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/* Priority Code Point */
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#define RTL8366_VMCR_PCP(_r) \
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((_r[RTL8366_VMCR_DOT1Q_REG] & RTL8366_VMCR_DOT1Q_PCP_MASK) \
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>> RTL8366_VMCR_DOT1Q_PCP_SHIFT)
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/* Member ports */
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#define RTL8366_VMCR_MEMBER(_r) \
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(_r[RTL8366_VMCR_MU_REG] & RTL8366_VMCR_MU_MEMBER_MASK)
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/* Untagged ports */
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#define RTL8366_VMCR_UNTAG(_r) \
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((_r[RTL8366_VMCR_MU_REG] & RTL8366_VMCR_MU_UNTAG_MASK) \
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>> RTL8366_VMCR_MU_UNTAG_SHIFT)
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/* Forwarding ID */
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#define RTL8366_VMCR_FID(_r) \
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(sc->chip_type == 0 ? (_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) : \
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((_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) \
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>> RTL8366_VMCR_FID_FID_SHIFT))
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/*
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* Port VLAN Control, 4 ports per register
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* Determines the VID for untagged ingress frames through
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* index into VMC.
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*/
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#define RTL8366_PVCR_BASE (sc->chip_type == 0 ? 0x0063 : 0x0058)
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#define RTL8366_PVCR_PORT_SHIFT 4
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#define RTL8366_PVCR_PORT_PERREG (16 / RTL8366_PVCR_PORT_SHIFT)
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#define RTL8366_PVCR_PORT_MASK 0x000f
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#define RTL8366_PVCR_REG(_port) \
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(RTL8366_PVCR_BASE + _port / (RTL8366_PVCR_PORT_PERREG))
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#define RTL8366_PVCR_VAL(_port, _pvlan) \
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((_pvlan & RTL8366_PVCR_PORT_MASK) << \
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((_port % RTL8366_PVCR_PORT_PERREG) * RTL8366_PVCR_PORT_SHIFT))
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#define RTL8366_PVCR_GET(_port, _val) \
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(((_val) >> ((_port % RTL8366_PVCR_PORT_PERREG) * RTL8366_PVCR_PORT_SHIFT)) & RTL8366_PVCR_PORT_MASK)
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/* Reset Control */
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#define RTL8366_RCR 0x0100
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#define RTL8366_RCR_HARD_RESET 0x0001
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#define RTL8366_RCR_SOFT_RESET 0x0002
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/* Chip Version Control: CHIP_VER[3:0] */
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#define RTL8366_CVCR (sc->chip_type == 0 ? 0x050A : 0x0104)
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/* Chip Identifier */
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#define RTL8366RB_CIR 0x0509
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#define RTL8366RB_CIR_ID8366RB 0x5937
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#define RTL8366SR_CIR 0x0105
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#define RTL8366SR_CIR_ID8366SR 0x8366
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/* VLAN Ingress Control 2: [5:0] */
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#define RTL8366_VIC2R 0x037f
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/* MIB registers */
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#define RTL8366_MCNT_BASE 0x1000
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#define RTL8366_MCTLR (sc->chip_type == 0 ? 0x13f0 : 0x11F0)
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#define RTL8366_MCTLR_BUSY 0x0001
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#define RTL8366_MCTLR_RESET 0x0002
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#define RTL8366_MCTLR_RESET_PORT_MASK 0x00fc
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#define RTL8366_MCTLR_RESET_ALL 0x0800
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#define RTL8366_MCNT(_port, _r) \
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(RTL8366_MCNT_BASE + 0x50 * (_port) + (_r))
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#define RTL8366_MCTLR_RESET_PORT(_p) \
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(1 << ((_p) + 2))
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/* PHY Access Control */
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#define RTL8366_PACR (sc->chip_type == 0 ? 0x8000 : 0x8028)
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#define RTL8366_PACR_WRITE 0x0000
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#define RTL8366_PACR_READ 0x0001
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/* PHY Access Data */
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#define RTL8366_PADR (sc->chip_type == 0 ? 0x8002 : 0x8029)
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#define RTL8366_PHYREG(phy, page, reg) \
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(0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))
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/* general characteristics of the chip */
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#define RTL8366_NUM_PHYS 5
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#define RTL8366_NUM_VLANS 16
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#define RTL8366_NUM_PHY_REG 32
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#endif
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