4853df5bb0
I have put it here, because I belive we could share some code among the various kinds of boot-code, whenever we get the time to look at it. Submitted by: Martin Renters
179 lines
5.2 KiB
C
179 lines
5.2 KiB
C
/**************************************************************************
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NETBOOT - BOOTP/TFTP Bootstrap Program
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Author: Martin Renters
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Date: Jun/94
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**************************************************************************/
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#define TRUE 1
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#define FALSE 0
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#define ETH_MIN_PACKET 64
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#define ETH_MAX_PACKET 1518
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#define VENDOR_NONE 0
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#define VENDOR_WD 1
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#define VENDOR_NOVELL 2
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#define FLAG_PIO 0x01
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#define FLAG_16BIT 0x02
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#define FLAG_790 0x04
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#define MEM_8192 32
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#define MEM_16384 64
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#define MEM_32768 128
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/**************************************************************************
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Western Digital/SMC Board Definitions
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**************************************************************************/
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#define WD_LOW_BASE 0x200
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#define WD_HIGH_BASE 0x3e0
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#ifndef WD_DEFAULT_MEM
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#define WD_DEFAULT_MEM 0xD0000
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#endif
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#define WD_NIC_ADDR 0x10
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/**************************************************************************
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Western Digital/SMC ASIC Addresses
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**************************************************************************/
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#define WD_MSR 0x00
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#define WD_ICR 0x01
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#define WD_IAR 0x02
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#define WD_BIO 0x03
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#define WD_IRR 0x04
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#define WD_LAAR 0x05
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#define WD_IJR 0x06
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#define WD_GP2 0x07
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#define WD_LAR 0x08
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#define WD_BID 0x0E
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#define WD_ICR_16BIT 0x01
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#define WD_MSR_MENB 0x40
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#define WD_LAAR_L16EN 0x40
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#define WD_LAAR_M16EN 0x80
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#define WD_SOFTCONFIG 0x20
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/**************************************************************************
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Western Digital/SMC Board Types
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**************************************************************************/
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#define TYPE_WD8003S 0x02
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#define TYPE_WD8003E 0x03
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#define TYPE_WD8013EBT 0x05
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#define TYPE_WD8003W 0x24
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#define TYPE_WD8003EB 0x25
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#define TYPE_WD8013W 0x26
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#define TYPE_WD8013EP 0x27
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#define TYPE_WD8013WC 0x28
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#define TYPE_WD8013EPC 0x29
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#define TYPE_SMC8216T 0x2a
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#define TYPE_SMC8216C 0x2b
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#define TYPE_SMC8013EBP 0x2c
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#ifdef INCLUDE_WD
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struct wd_board {
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char *name;
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char id;
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char flags;
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char memsize;
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} wd_boards[] = {
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{"WD8003S", TYPE_WD8003S, 0, MEM_8192},
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{"WD8003E", TYPE_WD8003E, 0, MEM_8192},
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{"WD8013EBT", TYPE_WD8013EBT, FLAG_16BIT, MEM_16384},
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{"WD8003W", TYPE_WD8003W, 0, MEM_8192},
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{"WD8003EB", TYPE_WD8003EB, 0, MEM_8192},
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{"WD8013W", TYPE_WD8013W, FLAG_16BIT, MEM_16384},
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{"WD8003EP/WD8013EP",
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TYPE_WD8013EP, 0, MEM_8192},
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{"WD8013WC", TYPE_WD8013WC, FLAG_16BIT, MEM_16384},
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{"WD8013EPC", TYPE_WD8013EPC, FLAG_16BIT, MEM_16384},
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{"SMC8216T", TYPE_SMC8216T, FLAG_16BIT | FLAG_790, MEM_16384},
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{"SMC8216C", TYPE_SMC8216C, FLAG_16BIT | FLAG_790, MEM_16384},
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{"SMC8013EBP", TYPE_SMC8013EBP,FLAG_16BIT, MEM_16384},
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{NULL, 0, 0}
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};
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#endif
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/**************************************************************************
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NE1000/2000 definitions
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**************************************************************************/
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#ifndef NE_BASE
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#define NE_BASE 0x320
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#endif
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#define NE_ASIC_OFFSET 0x10
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#define NE_RESET 0x0F /* Used to reset card */
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#define NE_DATA 0x00 /* Used to read/write NIC mem */
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/**************************************************************************
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8390 Register Definitions
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**************************************************************************/
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#define D8390_P0_COMMAND 0x00
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#define D8390_P0_PSTART 0x01
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#define D8390_P0_PSTOP 0x02
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#define D8390_P0_BOUND 0x03
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#define D8390_P0_TSR 0x04
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#define D8390_P0_TPSR 0x04
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#define D8390_P0_TBCR0 0x05
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#define D8390_P0_TBCR1 0x06
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#define D8390_P0_ISR 0x07
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#define D8390_P0_RSAR0 0x08
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#define D8390_P0_RSAR1 0x09
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#define D8390_P0_RBCR0 0x0A
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#define D8390_P0_RBCR1 0x0B
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#define D8390_P0_RSR 0x0C
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#define D8390_P0_RCR 0x0C
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#define D8390_P0_TCR 0x0D
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#define D8390_P0_DCR 0x0E
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#define D8390_P0_IMR 0x0F
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#define D8390_P1_COMMAND 0x00
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#define D8390_P1_PAR0 0x01
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#define D8390_P1_PAR1 0x02
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#define D8390_P1_PAR2 0x03
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#define D8390_P1_PAR3 0x04
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#define D8390_P1_PAR4 0x05
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#define D8390_P1_PAR5 0x06
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#define D8390_P1_CURR 0x07
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#define D8390_P1_MAR0 0x08
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#define D8390_COMMAND_PS0 0x0 /* Page 0 select */
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#define D8390_COMMAND_PS1 0x40 /* Page 1 select */
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#define D8390_COMMAND_PS2 0x80 /* Page 2 select */
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#define D8390_COMMAND_RD2 0x20 /* Remote DMA control */
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#define D8390_COMMAND_RD1 0x10
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#define D8390_COMMAND_RD0 0x08
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#define D8390_COMMAND_TXP 0x04 /* transmit packet */
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#define D8390_COMMAND_STA 0x02 /* start */
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#define D8390_COMMAND_STP 0x01 /* stop */
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#define D8390_RCR_MON 0x20 /* monitor mode */
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#define D8390_DCR_FT1 0x40
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#define D8390_DCR_LS 0x08 /* Loopback select */
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#define D8390_DCR_WTS 0x01 /* Word transfer select */
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#define D8390_ISR_PRX 0x01 /* successful recv */
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#define D8390_ISR_PTX 0x02 /* successful xmit */
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#define D8390_ISR_RXE 0x04 /* receive error */
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#define D8390_ISR_TXE 0x08 /* transmit error */
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#define D8390_ISR_OVW 0x10 /* Overflow */
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#define D8390_ISR_CNT 0x20 /* Counter overflow */
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#define D8390_ISR_RDC 0x40 /* Remote DMA complete */
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#define D8390_ISR_RST 0x80 /* reset */
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#define D8390_RSTAT_PRX 0x01 /* successful recv */
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#define D8390_RSTAT_CRC 0x02 /* CRC error */
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#define D8390_RSTAT_FAE 0x04 /* Frame alignment error */
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#define D8390_RSTAT_OVER 0x08 /* overflow */
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#define D8390_TXBUF_SIZE 6
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#define D8390_RXBUF_END 32
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struct ringbuffer {
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unsigned char status;
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unsigned char bound;
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unsigned short len;
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};
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