Emmanuel Vadot caecd45840 arm64: rockchip: rk3328_pll: Multiple improvement ... RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here, when switching PLL frequency, first switch it to slow mode. When set to slow mode the PLL clock will be the external oscillator. Changing the PLL parameters while its output is used can cause hang (sometimes). MFC after: 1 week		2019-02-26 13:16:05 +00:00
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acpica	arm64 acpi: Add support for IORT table	2019-02-07 02:30:33 +00:00
arm64	Enable enabling ASLR on non-x86 architectures.	2019-02-14 14:44:53 +00:00
cavium	Rename the ThunderX CPU identification macros to include the X. This is the	2018-06-13 12:17:11 +00:00
cloudabi32	Port cloudabi32.ko to FreeBSD/arm64.	2017-11-30 17:58:48 +00:00
cloudabi64	Correct some more places where TO_PTR() should be used.	2017-11-26 14:53:56 +00:00
conf	arm64: Fix compile when removing SOC_ROCKCHIP_* options	2019-02-10 08:14:06 +00:00
coresight	Fix one more OF_getprop_alloc instance missed in r332310	2018-04-08 23:17:51 +00:00
include	Add kernel support for Intel userspace protection keys feature on	2019-02-20 09:51:13 +00:00
linux	Fix errno values returned from DUMMY_XATTR linuxulator calls	2019-01-11 07:58:25 +00:00
qualcomm	Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.	2018-04-10 12:53:48 +00:00
rockchip	arm64: rockchip: rk3328_pll: Multiple improvement	2019-02-26 13:16:05 +00:00