cbf2160e81
The full system memory barrier around a TLB invalidation is stricter than required. It needs to wait on accesses to main memory, with just the weaker store variant before the invalidate. As such use the dsb istst, tlbi, dlb ish sequence already used in pmap. The tlbi instruction in this sequence is also unnecessarily using a broadcast invalidate when it just needs to invalidate the local CPUs TLB. Switch to a non-broadcast variant of this instruction. Sponsored by: DARPA, AFRL |
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