570255d8a5
It turns LBC control registers were not programmed correctly on MPC85XX. We were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was erroneously added during offset calculations. Effectively the state of LBC control registers was not altered by the kernel initialization code, but everything worked as long as we coincided to use the same settings (LBC decode windows) as firmware has initialized. Submitted by: Lukasz Wojcik Reviewed by: marcel Approved by: re (kensmith) Obtained from: Semihalf
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/*-
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* Copyright (c) 2006-2008, Juniper Networks, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_LBC_H_
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#define _MACHINE_LBC_H_
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#define LBC_IVAR_DEVTYPE 1
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/* Maximum number of devices on Local Bus */
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#define LBC_DEV_MAX 8
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/* Device types. */
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#define LBC_DEVTYPE_CFI 1
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#define LBC_DEVTYPE_RTC 2
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/* Local access registers */
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#define LBC85XX_BR(n) (8 * n)
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#define LBC85XX_OR(n) (4 + (8 * n))
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#define LBC85XX_LBCR (0xd0)
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#define LBC85XX_LCRR (0xd4)
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/* LBC machine select */
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#define LBCRES_MSEL_GPCM 0
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#define LBCRES_MSEL_FCM 1
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#define LBCRES_MSEL_UPMA 8
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#define LBCRES_MSEL_UPMB 9
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#define LBCRES_MSEL_UPMC 10
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/* LBC data error checking modes */
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#define LBCRES_DECC_DISABLED 0
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#define LBCRES_DECC_NORMAL 1
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#define LBCRES_DECC_RMW 2
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/* LBC atomic operation modes */
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#define LBCRES_ATOM_DISABLED 0
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#define LBCRES_ATOM_RAWA 1
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#define LBCRES_ATOM_WARA 2
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struct lbc_resource {
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int lbr_devtype; /* LBC device type */
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int lbr_unit; /* Resource table entry number */
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vm_paddr_t lbr_base_addr; /* Device mem region base address */
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size_t lbr_size; /* Device mem region size */
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int lbr_port_size; /* Data bus width */
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uint8_t lbr_msel; /* LBC machine select */
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uint8_t lbr_decc; /* Data error checking mode */
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uint8_t lbr_atom; /* Atomic operation mode */
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uint8_t lbr_wp; /* Write protect */
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};
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extern const struct lbc_resource mpc85xx_lbc_resources[];
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#endif /* _MACHINE_LBC_H_ */
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