1168 lines
39 KiB
C
1168 lines
39 KiB
C
/*-
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* Copyright (c) 2002-2007 Neterion, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifdef XGE_DEBUG_FP
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#include <dev/nxge/include/xgehal-fifo.h>
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#endif
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t*
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__hal_fifo_txdl_priv(xge_hal_dtr_h dtrh)
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{
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xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t*)dtrh;
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xge_hal_fifo_txdl_priv_t *txdl_priv;
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xge_assert(txdp);
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txdl_priv = (xge_hal_fifo_txdl_priv_t *)
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(ulong_t)txdp->host_control;
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xge_assert(txdl_priv);
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xge_assert(txdl_priv->dma_object);
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xge_assert(txdl_priv->dma_addr);
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xge_assert(txdl_priv->dma_object->handle == txdl_priv->dma_handle);
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return txdl_priv;
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}
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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__hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
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u64 ctrl_1)
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{
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xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
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xge_hal_fifo_hw_pair_t *hw_pair = fifo->hw_pair;
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xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
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xge_hal_fifo_txdl_priv_t *txdl_priv;
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u64 ctrl;
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txdp->control_1 |= XGE_HAL_TXD_LIST_OWN_XENA;
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#ifdef XGE_DEBUG_ASSERT
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/* make sure Xena overwrites the (illegal) t_code value on completion */
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XGE_HAL_SET_TXD_T_CODE(txdp->control_1, XGE_HAL_TXD_T_CODE_UNUSED_5);
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#endif
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txdl_priv = __hal_fifo_txdl_priv(dtrh);
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#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
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/* sync the TxDL to device */
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xge_os_dma_sync(fifo->channel.pdev,
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txdl_priv->dma_handle,
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txdl_priv->dma_addr,
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txdl_priv->dma_offset,
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txdl_priv->frags << 5 /* sizeof(xge_hal_fifo_txd_t) */,
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XGE_OS_DMA_DIR_TODEVICE);
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#endif
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/* write the pointer first */
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xge_os_pio_mem_write64(fifo->channel.pdev,
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fifo->channel.regh1,
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txdl_priv->dma_addr,
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&hw_pair->txdl_pointer);
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/* spec: 0x00 = 1 TxD in the list */
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ctrl = XGE_HAL_TX_FIFO_LAST_TXD_NUM(txdl_priv->frags - 1);
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ctrl |= ctrl_1;
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ctrl |= fifo->no_snoop_bits;
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if (txdp->control_1 & XGE_HAL_TXD_LSO_COF_CTRL(XGE_HAL_TXD_TCP_LSO)) {
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ctrl |= XGE_HAL_TX_FIFO_SPECIAL_FUNC;
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}
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/*
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* according to the XENA spec:
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*
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* It is important to note that pointers and list control words are
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* always written in pairs: in the first write, the host must write a
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* pointer, and in the second write, it must write the list control
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* word. Any other access will result in an error. Also, all 16 bytes
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* of the pointer/control structure must be written, including any
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* reserved bytes.
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*/
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xge_os_wmb();
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/*
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* we want touch work_arr in order with ownership bit set to HW
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*/
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__hal_channel_dtr_post(channelh, dtrh);
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xge_os_pio_mem_write64(fifo->channel.pdev, fifo->channel.regh1,
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ctrl, &hw_pair->list_control);
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xge_debug_fifo(XGE_TRACE, "posted txdl 0x"XGE_OS_LLXFMT" ctrl 0x"XGE_OS_LLXFMT" "
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"into 0x"XGE_OS_LLXFMT"", (unsigned long long)txdl_priv->dma_addr,
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(unsigned long long)ctrl,
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(unsigned long long)(ulong_t)&hw_pair->txdl_pointer);
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#ifdef XGE_HAL_FIFO_DUMP_TXD
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xge_os_printf(""XGE_OS_LLXFMT":"XGE_OS_LLXFMT":"XGE_OS_LLXFMT":"
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XGE_OS_LLXFMT" dma "XGE_OS_LLXFMT,
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txdp->control_1, txdp->control_2, txdp->buffer_pointer,
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txdp->host_control, txdl_priv->dma_addr);
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#endif
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fifo->channel.stats.total_posts++;
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fifo->channel.usage_cnt++;
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if (fifo->channel.stats.usage_max < fifo->channel.usage_cnt)
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fifo->channel.stats.usage_max = fifo->channel.usage_cnt;
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}
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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__hal_fifo_txdl_free_many(xge_hal_channel_h channelh,
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xge_hal_fifo_txd_t *txdp, int list_size, int frags)
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{
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xge_hal_fifo_txdl_priv_t *current_txdl_priv;
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xge_hal_fifo_txdl_priv_t *next_txdl_priv;
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int invalid_frags = frags % list_size;
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if (invalid_frags){
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xge_debug_fifo(XGE_ERR,
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"freeing corrupt dtrh %p, fragments %d list size %d",
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txdp, frags, list_size);
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xge_assert(invalid_frags == 0);
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}
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while(txdp){
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xge_debug_fifo(XGE_TRACE,
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"freeing linked dtrh %p, fragments %d list size %d",
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txdp, frags, list_size);
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current_txdl_priv = __hal_fifo_txdl_priv(txdp);
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#if defined(XGE_DEBUG_ASSERT) && defined(XGE_OS_MEMORY_CHECK)
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current_txdl_priv->allocated = 0;
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#endif
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__hal_channel_dtr_free(channelh, txdp);
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next_txdl_priv = current_txdl_priv->next_txdl_priv;
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xge_assert(frags);
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frags -= list_size;
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if (next_txdl_priv) {
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current_txdl_priv->next_txdl_priv = NULL;
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txdp = next_txdl_priv->first_txdp;
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}
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else {
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xge_debug_fifo(XGE_TRACE,
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"freed linked dtrh fragments %d list size %d",
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frags, list_size);
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break;
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}
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}
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xge_assert(frags == 0)
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}
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
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__hal_fifo_txdl_restore_many(xge_hal_channel_h channelh,
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xge_hal_fifo_txd_t *txdp, int txdl_count)
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{
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xge_hal_fifo_txdl_priv_t *current_txdl_priv;
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xge_hal_fifo_txdl_priv_t *next_txdl_priv;
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int i = txdl_count;
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xge_assert(((xge_hal_channel_t *)channelh)->reserve_length +
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txdl_count <= ((xge_hal_channel_t *)channelh)->reserve_initial);
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current_txdl_priv = __hal_fifo_txdl_priv(txdp);
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do{
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xge_assert(i);
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#if defined(XGE_DEBUG_ASSERT) && defined(XGE_OS_MEMORY_CHECK)
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current_txdl_priv->allocated = 0;
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#endif
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next_txdl_priv = current_txdl_priv->next_txdl_priv;
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txdp = current_txdl_priv->first_txdp;
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current_txdl_priv->next_txdl_priv = NULL;
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__hal_channel_dtr_restore(channelh, (xge_hal_dtr_h )txdp, --i);
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xge_debug_fifo(XGE_TRACE,
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"dtrh %p restored at offset %d", txdp, i);
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current_txdl_priv = next_txdl_priv;
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} while(current_txdl_priv);
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__hal_channel_dtr_restore(channelh, NULL, txdl_count);
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}
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/**
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* xge_hal_fifo_dtr_private - Retrieve per-descriptor private data.
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* @channelh: Channel handle.
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* @dtrh: Descriptor handle.
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*
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* Retrieve per-descriptor private data.
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* Note that ULD requests per-descriptor space via
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* xge_hal_channel_open().
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*
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* Returns: private ULD data associated with the descriptor.
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* Usage: See ex_xmit{} and ex_tx_compl{}.
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*/
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO void*
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xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh)
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{
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xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
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return ((char *)(ulong_t)txdp->host_control) +
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sizeof(xge_hal_fifo_txdl_priv_t);
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}
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/**
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* xge_hal_fifo_dtr_buffer_cnt - Get number of buffers carried by the
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* descriptor.
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* @dtrh: Descriptor handle.
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*
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* Returns: Number of buffers stored in the given descriptor. Can be used
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* _after_ the descriptor is set up for posting (see
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* xge_hal_fifo_dtr_post()) and _before_ it is deallocated (see
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* xge_hal_fifo_dtr_free()).
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*
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*/
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO int
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xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh)
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{
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xge_hal_fifo_txdl_priv_t *txdl_priv;
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txdl_priv = __hal_fifo_txdl_priv(dtrh);
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return txdl_priv->frags;
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}
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/**
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* xge_hal_fifo_dtr_reserve_many- Reserve fifo descriptors which span more
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* than single txdl.
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* @channelh: Channel handle.
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* @dtrh: Reserved descriptor. On success HAL fills this "out" parameter
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* with a valid handle.
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* @frags: minimum number of fragments to be reserved.
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*
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* Reserve TxDL(s) (that is, fifo descriptor)
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* for the subsequent filling-in by upper layerdriver (ULD))
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* and posting on the corresponding channel (@channelh)
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* via xge_hal_fifo_dtr_post().
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*
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* Returns: XGE_HAL_OK - success;
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* XGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
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*
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* See also: xge_hal_fifo_dtr_reserve_sp(), xge_hal_fifo_dtr_free(),
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* xge_hal_ring_dtr_reserve(), xge_hal_status_e{}.
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* Usage: See ex_xmit{}.
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*/
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh,
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xge_hal_dtr_h *dtrh, const int frags)
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{
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xge_hal_status_e status = XGE_HAL_OK;
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int alloc_frags = 0, dang_frags = 0;
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xge_hal_fifo_txd_t *curr_txdp = NULL;
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xge_hal_fifo_txd_t *next_txdp;
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xge_hal_fifo_txdl_priv_t *next_txdl_priv, *curr_txdl_priv = NULL;
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xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
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int max_frags = fifo->config->max_frags;
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xge_hal_dtr_h dang_dtrh = NULL;
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#if defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
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unsigned long flags=0;
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#endif
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xge_debug_fifo(XGE_TRACE, "dtr_reserve_many called for frags %d",
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frags);
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xge_assert(frags < (fifo->txdl_per_memblock * max_frags));
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#if defined(XGE_HAL_TX_MULTI_RESERVE)
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xge_os_spin_lock(&fifo->channel.reserve_lock);
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#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
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xge_os_spin_lock_irq(&fifo->channel.reserve_lock, flags);
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#endif
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while(alloc_frags < frags) {
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status = __hal_channel_dtr_alloc(channelh,
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(xge_hal_dtr_h *)(void*)&next_txdp);
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if (status != XGE_HAL_OK){
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xge_debug_fifo(XGE_ERR,
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"failed to allocate linked fragments rc %d",
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status);
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xge_assert(status == XGE_HAL_INF_OUT_OF_DESCRIPTORS);
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if (*dtrh) {
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xge_assert(alloc_frags/max_frags);
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__hal_fifo_txdl_restore_many(channelh,
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(xge_hal_fifo_txd_t *) *dtrh, alloc_frags/max_frags);
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}
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if (dang_dtrh) {
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xge_assert(dang_frags/max_frags);
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__hal_fifo_txdl_restore_many(channelh,
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(xge_hal_fifo_txd_t *) dang_dtrh, dang_frags/max_frags);
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}
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break;
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}
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xge_debug_fifo(XGE_TRACE, "allocated linked dtrh %p"
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" for frags %d", next_txdp, frags);
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next_txdl_priv = __hal_fifo_txdl_priv(next_txdp);
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xge_assert(next_txdl_priv);
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xge_assert(next_txdl_priv->first_txdp == next_txdp);
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next_txdl_priv->dang_txdl = NULL;
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next_txdl_priv->dang_frags = 0;
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next_txdl_priv->next_txdl_priv = NULL;
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#if defined(XGE_OS_MEMORY_CHECK)
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next_txdl_priv->allocated = 1;
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#endif
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if (!curr_txdp || !curr_txdl_priv) {
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curr_txdp = next_txdp;
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curr_txdl_priv = next_txdl_priv;
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*dtrh = (xge_hal_dtr_h)next_txdp;
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alloc_frags = max_frags;
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continue;
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}
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if (curr_txdl_priv->memblock ==
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next_txdl_priv->memblock) {
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xge_debug_fifo(XGE_TRACE,
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"linking dtrh %p, with %p",
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*dtrh, next_txdp);
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xge_assert (next_txdp ==
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curr_txdp + max_frags);
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alloc_frags += max_frags;
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curr_txdl_priv->next_txdl_priv = next_txdl_priv;
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}
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else {
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xge_assert(*dtrh);
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xge_assert(dang_dtrh == NULL);
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dang_dtrh = *dtrh;
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dang_frags = alloc_frags;
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xge_debug_fifo(XGE_TRACE,
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"dangling dtrh %p, linked with dtrh %p",
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*dtrh, next_txdp);
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next_txdl_priv->dang_txdl = (xge_hal_fifo_txd_t *) *dtrh;
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next_txdl_priv->dang_frags = alloc_frags;
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alloc_frags = max_frags;
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*dtrh = next_txdp;
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}
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curr_txdp = next_txdp;
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curr_txdl_priv = next_txdl_priv;
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}
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#if defined(XGE_HAL_TX_MULTI_RESERVE)
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xge_os_spin_unlock(&fifo->channel.reserve_lock);
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#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
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xge_os_spin_unlock_irq(&fifo->channel.reserve_lock, flags);
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#endif
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if (status == XGE_HAL_OK) {
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xge_hal_fifo_txdl_priv_t * txdl_priv;
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xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)*dtrh;
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xge_hal_stats_channel_info_t *statsp = &fifo->channel.stats;
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txdl_priv = __hal_fifo_txdl_priv(txdp);
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/* reset the TxDL's private */
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txdl_priv->align_dma_offset = 0;
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txdl_priv->align_vaddr_start = txdl_priv->align_vaddr;
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txdl_priv->align_used_frags = 0;
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txdl_priv->frags = 0;
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txdl_priv->bytes_sent = 0;
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txdl_priv->alloc_frags = alloc_frags;
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/* reset TxD0 */
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txdp->control_1 = txdp->control_2 = 0;
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#if defined(XGE_OS_MEMORY_CHECK)
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txdl_priv->allocated = 1;
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#endif
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/* update statistics */
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statsp->total_posts_dtrs_many++;
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statsp->total_posts_frags_many += txdl_priv->alloc_frags;
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if (txdl_priv->dang_frags){
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statsp->total_posts_dang_dtrs++;
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statsp->total_posts_dang_frags += txdl_priv->dang_frags;
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}
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}
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return status;
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}
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/**
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* xge_hal_fifo_dtr_reserve - Reserve fifo descriptor.
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* @channelh: Channel handle.
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* @dtrh: Reserved descriptor. On success HAL fills this "out" parameter
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* with a valid handle.
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*
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* Reserve a single TxDL (that is, fifo descriptor)
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* for the subsequent filling-in by upper layerdriver (ULD))
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* and posting on the corresponding channel (@channelh)
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* via xge_hal_fifo_dtr_post().
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*
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* Note: it is the responsibility of ULD to reserve multiple descriptors
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* for lengthy (e.g., LSO) transmit operation. A single fifo descriptor
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* carries up to configured number (fifo.max_frags) of contiguous buffers.
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*
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* Returns: XGE_HAL_OK - success;
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* XGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
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*
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* See also: xge_hal_fifo_dtr_reserve_sp(), xge_hal_fifo_dtr_free(),
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* xge_hal_ring_dtr_reserve(), xge_hal_status_e{}.
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* Usage: See ex_xmit{}.
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*/
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__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
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xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh)
|
|
{
|
|
xge_hal_status_e status;
|
|
#if defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
|
|
unsigned long flags=0;
|
|
#endif
|
|
|
|
#if defined(XGE_HAL_TX_MULTI_RESERVE)
|
|
xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->reserve_lock);
|
|
#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
|
|
xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->reserve_lock,
|
|
flags);
|
|
#endif
|
|
|
|
status = __hal_channel_dtr_alloc(channelh, dtrh);
|
|
|
|
#if defined(XGE_HAL_TX_MULTI_RESERVE)
|
|
xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->reserve_lock);
|
|
#elif defined(XGE_HAL_TX_MULTI_RESERVE_IRQ)
|
|
xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->reserve_lock,
|
|
flags);
|
|
#endif
|
|
|
|
if (status == XGE_HAL_OK) {
|
|
xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)*dtrh;
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(txdp);
|
|
|
|
/* reset the TxDL's private */
|
|
txdl_priv->align_dma_offset = 0;
|
|
txdl_priv->align_vaddr_start = txdl_priv->align_vaddr;
|
|
txdl_priv->align_used_frags = 0;
|
|
txdl_priv->frags = 0;
|
|
txdl_priv->alloc_frags =
|
|
((xge_hal_fifo_t *)channelh)->config->max_frags;
|
|
txdl_priv->dang_txdl = NULL;
|
|
txdl_priv->dang_frags = 0;
|
|
txdl_priv->next_txdl_priv = NULL;
|
|
txdl_priv->bytes_sent = 0;
|
|
|
|
/* reset TxD0 */
|
|
txdp->control_1 = txdp->control_2 = 0;
|
|
|
|
#if defined(XGE_OS_MEMORY_CHECK)
|
|
txdl_priv->allocated = 1;
|
|
#endif
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_reserve_sp - Reserve fifo descriptor and store it in
|
|
* the ULD-provided "scratch" memory.
|
|
* @channelh: Channel handle.
|
|
* @dtr_sp_size: Size of the %dtr_sp "scratch pad" that HAL can use for TxDL.
|
|
* @dtr_sp: "Scratch pad" supplied by upper-layer driver (ULD).
|
|
*
|
|
* Reserve TxDL and fill-in ULD supplied "scratch pad". The difference
|
|
* between this API and xge_hal_fifo_dtr_reserve() is (possibly) -
|
|
* performance.
|
|
*
|
|
* If upper-layer uses ULP-defined commands, and if those commands have enough
|
|
* space for HAL/Xframe descriptors - tnan it is better (read: faster) to fit
|
|
* all the per-command information into one command, which is typically
|
|
* one contiguous block.
|
|
*
|
|
* Note: Unlike xge_hal_fifo_dtr_reserve(), this function can be used to
|
|
* allocate a single descriptor for transmit operation.
|
|
*
|
|
* See also: xge_hal_fifo_dtr_reserve(), xge_hal_fifo_dtr_free(),
|
|
* xge_hal_ring_dtr_reserve(), xge_hal_status_e{}.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
|
|
xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channelh, int dtr_sp_size,
|
|
xge_hal_dtr_h dtr_sp)
|
|
{
|
|
/* FIXME: implement */
|
|
return XGE_HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_post - Post descriptor on the fifo channel.
|
|
* @channelh: Channel handle.
|
|
* @dtrh: Descriptor obtained via xge_hal_fifo_dtr_reserve() or
|
|
* xge_hal_fifo_dtr_reserve_sp()
|
|
* @frags: Number of contiguous buffers that are part of a single
|
|
* transmit operation.
|
|
*
|
|
* Post descriptor on the 'fifo' type channel for transmission.
|
|
* Prior to posting the descriptor should be filled in accordance with
|
|
* Host/Xframe interface specification for a given service (LL, etc.).
|
|
*
|
|
* See also: xge_hal_fifo_dtr_post_many(), xge_hal_ring_dtr_post().
|
|
* Usage: See ex_xmit{}.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh)
|
|
{
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
xge_hal_fifo_txd_t *txdp_last;
|
|
xge_hal_fifo_txd_t *txdp_first;
|
|
#if defined(XGE_HAL_TX_MULTI_POST_IRQ)
|
|
unsigned long flags = 0;
|
|
#endif
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(dtrh);
|
|
|
|
txdp_first = (xge_hal_fifo_txd_t *)dtrh;
|
|
txdp_first->control_1 |= XGE_HAL_TXD_GATHER_CODE_FIRST;
|
|
txdp_first->control_2 |= fifo->interrupt_type;
|
|
|
|
txdp_last = (xge_hal_fifo_txd_t *)dtrh + (txdl_priv->frags - 1);
|
|
txdp_last->control_1 |= XGE_HAL_TXD_GATHER_CODE_LAST;
|
|
|
|
#if defined(XGE_HAL_TX_MULTI_POST)
|
|
xge_os_spin_lock(fifo->post_lock_ptr);
|
|
#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
|
|
xge_os_spin_lock_irq(fifo->post_lock_ptr, flags);
|
|
#endif
|
|
|
|
__hal_fifo_dtr_post_single(channelh, dtrh,
|
|
(u64)(XGE_HAL_TX_FIFO_FIRST_LIST | XGE_HAL_TX_FIFO_LAST_LIST));
|
|
|
|
#if defined(XGE_HAL_TX_MULTI_POST)
|
|
xge_os_spin_unlock(fifo->post_lock_ptr);
|
|
#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
|
|
xge_os_spin_unlock_irq(fifo->post_lock_ptr, flags);
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_post_many - Post multiple descriptors on fifo
|
|
* channel.
|
|
* @channelh: Channel to post descriptor.
|
|
* @num: Number of descriptors (i.e., fifo TxDLs) in the %dtrs[].
|
|
* @dtrs: Descriptors obtained via xge_hal_fifo_dtr_reserve().
|
|
* @frags_arr: Number of fragments carried @dtrs descriptors.
|
|
* Note that frag_arr[i] corresponds to descriptor dtrs[i].
|
|
*
|
|
* Post multi-descriptor on the fifo channel. The operation is atomic:
|
|
* all descriptrs are posted on the channel "back-to-back' without
|
|
* letting other posts (possibly driven by multiple transmitting threads)
|
|
* to interleave.
|
|
*
|
|
* See also: xge_hal_fifo_dtr_post(), xge_hal_ring_dtr_post().
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num,
|
|
xge_hal_dtr_h dtrs[])
|
|
{
|
|
int i;
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
xge_hal_fifo_txd_t *txdp_last;
|
|
xge_hal_fifo_txd_t *txdp_first;
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv_last;
|
|
#if defined(XGE_HAL_TX_MULTI_POST_IRQ)
|
|
unsigned long flags = 0;
|
|
#endif
|
|
|
|
xge_assert(num > 1);
|
|
|
|
txdp_first = (xge_hal_fifo_txd_t *)dtrs[0];
|
|
txdp_first->control_1 |= XGE_HAL_TXD_GATHER_CODE_FIRST;
|
|
txdp_first->control_2 |= fifo->interrupt_type;
|
|
|
|
txdl_priv_last = __hal_fifo_txdl_priv(dtrs[num-1]);
|
|
txdp_last = (xge_hal_fifo_txd_t *)dtrs[num-1] +
|
|
(txdl_priv_last->frags - 1);
|
|
txdp_last->control_1 |= XGE_HAL_TXD_GATHER_CODE_LAST;
|
|
|
|
#if defined(XGE_HAL_TX_MULTI_POST)
|
|
xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->post_lock);
|
|
#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
|
|
xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->post_lock,
|
|
flags);
|
|
#endif
|
|
|
|
for (i=0; i<num; i++) {
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
u64 val64;
|
|
xge_hal_dtr_h dtrh = dtrs[i];
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(dtrh);
|
|
txdl_priv = txdl_priv; /* Cheat lint */
|
|
|
|
val64 = 0;
|
|
if (i == 0) {
|
|
val64 |= XGE_HAL_TX_FIFO_FIRST_LIST;
|
|
} else if (i == num -1) {
|
|
val64 |= XGE_HAL_TX_FIFO_LAST_LIST;
|
|
}
|
|
|
|
val64 |= XGE_HAL_TX_FIFO_SPECIAL_FUNC;
|
|
__hal_fifo_dtr_post_single(channelh, dtrh, val64);
|
|
}
|
|
|
|
#if defined(XGE_HAL_TX_MULTI_POST)
|
|
xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->post_lock);
|
|
#elif defined(XGE_HAL_TX_MULTI_POST_IRQ)
|
|
xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->post_lock,
|
|
flags);
|
|
#endif
|
|
|
|
fifo->channel.stats.total_posts_many++;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_next_completed - Retrieve next completed descriptor.
|
|
* @channelh: Channel handle.
|
|
* @dtrh: Descriptor handle. Returned by HAL.
|
|
* @t_code: Transfer code, as per Xframe User Guide,
|
|
* Transmit Descriptor Format.
|
|
* Returned by HAL.
|
|
*
|
|
* Retrieve the _next_ completed descriptor.
|
|
* HAL uses channel callback (*xge_hal_channel_callback_f) to notifiy
|
|
* upper-layer driver (ULD) of new completed descriptors. After that
|
|
* the ULD can use xge_hal_fifo_dtr_next_completed to retrieve the rest
|
|
* completions (the very first completion is passed by HAL via
|
|
* xge_hal_channel_callback_f).
|
|
*
|
|
* Implementation-wise, the upper-layer driver is free to call
|
|
* xge_hal_fifo_dtr_next_completed either immediately from inside the
|
|
* channel callback, or in a deferred fashion and separate (from HAL)
|
|
* context.
|
|
*
|
|
* Non-zero @t_code means failure to process the descriptor.
|
|
* The failure could happen, for instance, when the link is
|
|
* down, in which case Xframe completes the descriptor because it
|
|
* is not able to send the data out.
|
|
*
|
|
* For details please refer to Xframe User Guide.
|
|
*
|
|
* Returns: XGE_HAL_OK - success.
|
|
* XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
|
|
* are currently available for processing.
|
|
*
|
|
* See also: xge_hal_channel_callback_f{},
|
|
* xge_hal_ring_dtr_next_completed().
|
|
* Usage: See ex_tx_compl{}.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
|
|
xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh,
|
|
xge_hal_dtr_h *dtrh, u8 *t_code)
|
|
{
|
|
xge_hal_fifo_txd_t *txdp;
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
#endif
|
|
|
|
__hal_channel_dtr_try_complete(channelh, dtrh);
|
|
txdp = (xge_hal_fifo_txd_t *)*dtrh;
|
|
if (txdp == NULL) {
|
|
return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
|
|
}
|
|
|
|
#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
|
|
txdl_priv = __hal_fifo_txdl_priv(txdp);
|
|
|
|
/* sync TxDL to read the ownership
|
|
*
|
|
* Note: 16bytes means Control_1 & Control_2 */
|
|
xge_os_dma_sync(fifo->channel.pdev,
|
|
txdl_priv->dma_handle,
|
|
txdl_priv->dma_addr,
|
|
txdl_priv->dma_offset,
|
|
16,
|
|
XGE_OS_DMA_DIR_FROMDEVICE);
|
|
#endif
|
|
|
|
/* check whether host owns it */
|
|
if ( !(txdp->control_1 & XGE_HAL_TXD_LIST_OWN_XENA) ) {
|
|
|
|
xge_assert(txdp->host_control!=0);
|
|
|
|
__hal_channel_dtr_complete(channelh);
|
|
|
|
*t_code = (u8)XGE_HAL_GET_TXD_T_CODE(txdp->control_1);
|
|
|
|
/* see XGE_HAL_SET_TXD_T_CODE() above.. */
|
|
xge_assert(*t_code != XGE_HAL_TXD_T_CODE_UNUSED_5);
|
|
|
|
if (fifo->channel.usage_cnt > 0)
|
|
fifo->channel.usage_cnt--;
|
|
|
|
return XGE_HAL_OK;
|
|
}
|
|
|
|
/* no more completions */
|
|
*dtrh = 0;
|
|
return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_free - Free descriptor.
|
|
* @channelh: Channel handle.
|
|
* @dtr: Descriptor handle.
|
|
*
|
|
* Free the reserved descriptor. This operation is "symmetrical" to
|
|
* xge_hal_fifo_dtr_reserve or xge_hal_fifo_dtr_reserve_sp.
|
|
* The "free-ing" completes the descriptor's lifecycle.
|
|
*
|
|
* After free-ing (see xge_hal_fifo_dtr_free()) the descriptor again can
|
|
* be:
|
|
*
|
|
* - reserved (xge_hal_fifo_dtr_reserve);
|
|
*
|
|
* - posted (xge_hal_fifo_dtr_post);
|
|
*
|
|
* - completed (xge_hal_fifo_dtr_next_completed);
|
|
*
|
|
* - and recycled again (xge_hal_fifo_dtr_free).
|
|
*
|
|
* For alternative state transitions and more details please refer to
|
|
* the design doc.
|
|
*
|
|
* See also: xge_hal_ring_dtr_free(), xge_hal_fifo_dtr_reserve().
|
|
* Usage: See ex_tx_compl{}.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr)
|
|
{
|
|
#if defined(XGE_HAL_TX_MULTI_FREE_IRQ)
|
|
unsigned long flags = 0;
|
|
#endif
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv = __hal_fifo_txdl_priv(
|
|
(xge_hal_fifo_txd_t *)dtr);
|
|
int max_frags = ((xge_hal_fifo_t *)channelh)->config->max_frags;
|
|
#if defined(XGE_HAL_TX_MULTI_FREE)
|
|
xge_os_spin_lock(&((xge_hal_channel_t*)channelh)->free_lock);
|
|
#elif defined(XGE_HAL_TX_MULTI_FREE_IRQ)
|
|
xge_os_spin_lock_irq(&((xge_hal_channel_t*)channelh)->free_lock,
|
|
flags);
|
|
#endif
|
|
|
|
if (txdl_priv->alloc_frags > max_frags) {
|
|
xge_hal_fifo_txd_t *dang_txdp = (xge_hal_fifo_txd_t *)
|
|
txdl_priv->dang_txdl;
|
|
int dang_frags = txdl_priv->dang_frags;
|
|
int alloc_frags = txdl_priv->alloc_frags;
|
|
txdl_priv->dang_txdl = NULL;
|
|
txdl_priv->dang_frags = 0;
|
|
txdl_priv->alloc_frags = 0;
|
|
/* dtrh must have a linked list of dtrh */
|
|
xge_assert(txdl_priv->next_txdl_priv);
|
|
|
|
/* free any dangling dtrh first */
|
|
if (dang_txdp) {
|
|
xge_debug_fifo(XGE_TRACE,
|
|
"freeing dangled dtrh %p for %d fragments",
|
|
dang_txdp, dang_frags);
|
|
__hal_fifo_txdl_free_many(channelh, dang_txdp,
|
|
max_frags, dang_frags);
|
|
}
|
|
|
|
/* now free the reserved dtrh list */
|
|
xge_debug_fifo(XGE_TRACE,
|
|
"freeing dtrh %p list of %d fragments", dtr,
|
|
alloc_frags);
|
|
__hal_fifo_txdl_free_many(channelh,
|
|
(xge_hal_fifo_txd_t *)dtr, max_frags,
|
|
alloc_frags);
|
|
}
|
|
else
|
|
__hal_channel_dtr_free(channelh, dtr);
|
|
|
|
((xge_hal_channel_t *)channelh)->poll_bytes += txdl_priv->bytes_sent;
|
|
|
|
#if defined(XGE_DEBUG_ASSERT) && defined(XGE_OS_MEMORY_CHECK)
|
|
__hal_fifo_txdl_priv(dtr)->allocated = 0;
|
|
#endif
|
|
|
|
#if defined(XGE_HAL_TX_MULTI_FREE)
|
|
xge_os_spin_unlock(&((xge_hal_channel_t*)channelh)->free_lock);
|
|
#elif defined(XGE_HAL_TX_MULTI_FREE_IRQ)
|
|
xge_os_spin_unlock_irq(&((xge_hal_channel_t*)channelh)->free_lock,
|
|
flags);
|
|
#endif
|
|
}
|
|
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_buffer_set_aligned - Align transmit buffer and fill
|
|
* in fifo descriptor.
|
|
* @channelh: Channel handle.
|
|
* @dtrh: Descriptor handle.
|
|
* @frag_idx: Index of the data buffer in the caller's scatter-gather list
|
|
* (of buffers).
|
|
* @vaddr: Virtual address of the data buffer.
|
|
* @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
|
|
* @size: Size of the data buffer (in bytes).
|
|
* @misaligned_size: Size (in bytes) of the misaligned portion of the
|
|
* data buffer. Calculated by the caller, based on the platform/OS/other
|
|
* specific criteria, which is outside of HAL's domain. See notes below.
|
|
*
|
|
* This API is part of the transmit descriptor preparation for posting
|
|
* (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include
|
|
* xge_hal_fifo_dtr_mss_set() and xge_hal_fifo_dtr_cksum_set_bits().
|
|
* All three APIs fill in the fields of the fifo descriptor,
|
|
* in accordance with the Xframe specification.
|
|
* On the PCI-X based systems aligning transmit data typically provides better
|
|
* transmit performance. The typical alignment granularity: L2 cacheline size.
|
|
* However, HAL does not make assumptions in terms of the alignment granularity;
|
|
* this is specified via additional @misaligned_size parameter described above.
|
|
* Prior to calling xge_hal_fifo_dtr_buffer_set_aligned(),
|
|
* ULD is supposed to check alignment of a given fragment/buffer. For this HAL
|
|
* provides a separate xge_hal_check_alignment() API sufficient to cover
|
|
* most (but not all) possible alignment criteria.
|
|
* If the buffer appears to be aligned, the ULD calls
|
|
* xge_hal_fifo_dtr_buffer_set().
|
|
* Otherwise, ULD calls xge_hal_fifo_dtr_buffer_set_aligned().
|
|
*
|
|
* Note; This API is a "superset" of xge_hal_fifo_dtr_buffer_set(). In
|
|
* addition to filling in the specified descriptor it aligns transmit data on
|
|
* the specified boundary.
|
|
* Note: Decision on whether to align or not to align a given contiguous
|
|
* transmit buffer is outside of HAL's domain. To this end ULD can use any
|
|
* programmable criteria, which can help to 1) boost transmit performance,
|
|
* and/or 2) provide a workaround for PCI bridge bugs, if any.
|
|
*
|
|
* See also: xge_hal_fifo_dtr_buffer_set(),
|
|
* xge_hal_check_alignment().
|
|
*
|
|
* See also: xge_hal_fifo_dtr_reserve(), xge_hal_fifo_dtr_post(),
|
|
* xge_hal_fifo_dtr_mss_set(), xge_hal_fifo_dtr_cksum_set_bits()
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
|
|
xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh,
|
|
xge_hal_dtr_h dtrh, int frag_idx, void *vaddr,
|
|
dma_addr_t dma_pointer, int size, int misaligned_size)
|
|
{
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
xge_hal_fifo_txd_t *txdp;
|
|
int remaining_size;
|
|
ptrdiff_t prev_boff;
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(dtrh);
|
|
txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags;
|
|
|
|
if (frag_idx != 0) {
|
|
txdp->control_1 = txdp->control_2 = 0;
|
|
}
|
|
|
|
/* On some systems buffer size could be zero.
|
|
* It is the responsibility of ULD and *not HAL* to
|
|
* detect it and skip it. */
|
|
xge_assert(size > 0);
|
|
xge_assert(frag_idx < txdl_priv->alloc_frags);
|
|
xge_assert(misaligned_size != 0 &&
|
|
misaligned_size <= fifo->config->alignment_size);
|
|
|
|
remaining_size = size - misaligned_size;
|
|
xge_assert(remaining_size >= 0);
|
|
|
|
xge_os_memcpy((char*)txdl_priv->align_vaddr_start,
|
|
vaddr, misaligned_size);
|
|
|
|
if (txdl_priv->align_used_frags >= fifo->config->max_aligned_frags) {
|
|
return XGE_HAL_ERR_OUT_ALIGNED_FRAGS;
|
|
}
|
|
|
|
/* setup new buffer */
|
|
prev_boff = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr;
|
|
txdp->buffer_pointer = (u64)txdl_priv->align_dma_addr + prev_boff;
|
|
txdp->control_1 |= XGE_HAL_TXD_BUFFER0_SIZE(misaligned_size);
|
|
txdl_priv->bytes_sent += misaligned_size;
|
|
fifo->channel.stats.total_buffers++;
|
|
txdl_priv->frags++;
|
|
txdl_priv->align_used_frags++;
|
|
txdl_priv->align_vaddr_start += fifo->config->alignment_size;
|
|
txdl_priv->align_dma_offset = 0;
|
|
|
|
#if defined(XGE_OS_DMA_REQUIRES_SYNC)
|
|
/* sync new buffer */
|
|
xge_os_dma_sync(fifo->channel.pdev,
|
|
txdl_priv->align_dma_handle,
|
|
txdp->buffer_pointer,
|
|
0,
|
|
misaligned_size,
|
|
XGE_OS_DMA_DIR_TODEVICE);
|
|
#endif
|
|
|
|
if (remaining_size) {
|
|
xge_assert(frag_idx < txdl_priv->alloc_frags);
|
|
txdp++;
|
|
txdp->buffer_pointer = (u64)dma_pointer +
|
|
misaligned_size;
|
|
txdp->control_1 =
|
|
XGE_HAL_TXD_BUFFER0_SIZE(remaining_size);
|
|
txdl_priv->bytes_sent += remaining_size;
|
|
txdp->control_2 = 0;
|
|
fifo->channel.stats.total_buffers++;
|
|
txdl_priv->frags++;
|
|
}
|
|
|
|
return XGE_HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_buffer_append - Append the contents of virtually
|
|
* contiguous data buffer to a single physically contiguous buffer.
|
|
* @channelh: Channel handle.
|
|
* @dtrh: Descriptor handle.
|
|
* @vaddr: Virtual address of the data buffer.
|
|
* @size: Size of the data buffer (in bytes).
|
|
*
|
|
* This API is part of the transmit descriptor preparation for posting
|
|
* (via xge_hal_fifo_dtr_post()).
|
|
* The main difference of this API wrt to the APIs
|
|
* xge_hal_fifo_dtr_buffer_set_aligned() is that this API appends the
|
|
* contents of virtually contiguous data buffers received from
|
|
* upper layer into a single physically contiguous data buffer and the
|
|
* device will do a DMA from this buffer.
|
|
*
|
|
* See Also: xge_hal_fifo_dtr_buffer_finalize(), xge_hal_fifo_dtr_buffer_set(),
|
|
* xge_hal_fifo_dtr_buffer_set_aligned().
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
|
|
xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
|
|
void *vaddr, int size)
|
|
{
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
ptrdiff_t used;
|
|
|
|
xge_assert(size > 0);
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(dtrh);
|
|
|
|
used = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr;
|
|
used += txdl_priv->align_dma_offset;
|
|
if (used + (unsigned int)size > (unsigned int)fifo->align_size)
|
|
return XGE_HAL_ERR_OUT_ALIGNED_FRAGS;
|
|
|
|
xge_os_memcpy((char*)txdl_priv->align_vaddr_start +
|
|
txdl_priv->align_dma_offset, vaddr, size);
|
|
|
|
fifo->channel.stats.copied_frags++;
|
|
|
|
txdl_priv->align_dma_offset += size;
|
|
return XGE_HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_buffer_finalize - Prepares a descriptor that contains the
|
|
* single physically contiguous buffer.
|
|
*
|
|
* @channelh: Channel handle.
|
|
* @dtrh: Descriptor handle.
|
|
* @frag_idx: Index of the data buffer in the Txdl list.
|
|
*
|
|
* This API in conjuction with xge_hal_fifo_dtr_buffer_append() prepares
|
|
* a descriptor that consists of a single physically contiguous buffer
|
|
* which inturn contains the contents of one or more virtually contiguous
|
|
* buffers received from the upper layer.
|
|
*
|
|
* See Also: xge_hal_fifo_dtr_buffer_append().
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
|
|
int frag_idx)
|
|
{
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
xge_hal_fifo_txd_t *txdp;
|
|
ptrdiff_t prev_boff;
|
|
|
|
xge_assert(frag_idx < fifo->config->max_frags);
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(dtrh);
|
|
txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags;
|
|
|
|
if (frag_idx != 0) {
|
|
txdp->control_1 = txdp->control_2 = 0;
|
|
}
|
|
|
|
prev_boff = txdl_priv->align_vaddr_start - txdl_priv->align_vaddr;
|
|
txdp->buffer_pointer = (u64)txdl_priv->align_dma_addr + prev_boff;
|
|
txdp->control_1 |=
|
|
XGE_HAL_TXD_BUFFER0_SIZE(txdl_priv->align_dma_offset);
|
|
txdl_priv->bytes_sent += (unsigned int)txdl_priv->align_dma_offset;
|
|
fifo->channel.stats.total_buffers++;
|
|
fifo->channel.stats.copied_buffers++;
|
|
txdl_priv->frags++;
|
|
txdl_priv->align_used_frags++;
|
|
|
|
#if defined(XGE_OS_DMA_REQUIRES_SYNC)
|
|
/* sync pre-mapped buffer */
|
|
xge_os_dma_sync(fifo->channel.pdev,
|
|
txdl_priv->align_dma_handle,
|
|
txdp->buffer_pointer,
|
|
0,
|
|
txdl_priv->align_dma_offset,
|
|
XGE_OS_DMA_DIR_TODEVICE);
|
|
#endif
|
|
|
|
/* increment vaddr_start for the next buffer_append() iteration */
|
|
txdl_priv->align_vaddr_start += txdl_priv->align_dma_offset;
|
|
txdl_priv->align_dma_offset = 0;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_buffer_set - Set transmit buffer pointer in the
|
|
* descriptor.
|
|
* @channelh: Channel handle.
|
|
* @dtrh: Descriptor handle.
|
|
* @frag_idx: Index of the data buffer in the caller's scatter-gather list
|
|
* (of buffers).
|
|
* @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
|
|
* @size: Size of the data buffer (in bytes).
|
|
*
|
|
* This API is part of the preparation of the transmit descriptor for posting
|
|
* (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include
|
|
* xge_hal_fifo_dtr_mss_set() and xge_hal_fifo_dtr_cksum_set_bits().
|
|
* All three APIs fill in the fields of the fifo descriptor,
|
|
* in accordance with the Xframe specification.
|
|
*
|
|
* See also: xge_hal_fifo_dtr_buffer_set_aligned(),
|
|
* xge_hal_check_alignment().
|
|
*
|
|
* See also: xge_hal_fifo_dtr_reserve(), xge_hal_fifo_dtr_post(),
|
|
* xge_hal_fifo_dtr_mss_set(), xge_hal_fifo_dtr_cksum_set_bits()
|
|
* Prepare transmit descriptor for transmission (via
|
|
* xge_hal_fifo_dtr_post()).
|
|
* See also: xge_hal_fifo_dtr_vlan_set().
|
|
* Note: Compare with xge_hal_fifo_dtr_buffer_set_aligned().
|
|
*
|
|
* Usage: See ex_xmit{}.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
|
|
int frag_idx, dma_addr_t dma_pointer, int size)
|
|
{
|
|
xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
|
|
xge_hal_fifo_txdl_priv_t *txdl_priv;
|
|
xge_hal_fifo_txd_t *txdp;
|
|
|
|
txdl_priv = __hal_fifo_txdl_priv(dtrh);
|
|
txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags;
|
|
|
|
if (frag_idx != 0) {
|
|
txdp->control_1 = txdp->control_2 = 0;
|
|
}
|
|
|
|
/* Note:
|
|
* it is the responsibility of upper layers and not HAL
|
|
* detect it and skip zero-size fragment
|
|
*/
|
|
xge_assert(size > 0);
|
|
xge_assert(frag_idx < txdl_priv->alloc_frags);
|
|
|
|
txdp->buffer_pointer = (u64)dma_pointer;
|
|
txdp->control_1 |= XGE_HAL_TXD_BUFFER0_SIZE(size);
|
|
txdl_priv->bytes_sent += size;
|
|
fifo->channel.stats.total_buffers++;
|
|
txdl_priv->frags++;
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_mss_set - Set MSS.
|
|
* @dtrh: Descriptor handle.
|
|
* @mss: MSS size for _this_ TCP connection. Passed by TCP stack down to the
|
|
* ULD, which in turn inserts the MSS into the @dtrh.
|
|
*
|
|
* This API is part of the preparation of the transmit descriptor for posting
|
|
* (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include
|
|
* xge_hal_fifo_dtr_buffer_set(), xge_hal_fifo_dtr_buffer_set_aligned(),
|
|
* and xge_hal_fifo_dtr_cksum_set_bits().
|
|
* All these APIs fill in the fields of the fifo descriptor,
|
|
* in accordance with the Xframe specification.
|
|
*
|
|
* See also: xge_hal_fifo_dtr_reserve(),
|
|
* xge_hal_fifo_dtr_post(), xge_hal_fifo_dtr_vlan_set().
|
|
* Usage: See ex_xmit{}.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss)
|
|
{
|
|
xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
|
|
|
|
txdp->control_1 |= XGE_HAL_TXD_LSO_COF_CTRL(XGE_HAL_TXD_TCP_LSO);
|
|
txdp->control_1 |= XGE_HAL_TXD_TCP_LSO_MSS(mss);
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_cksum_set_bits - Offload checksum.
|
|
* @dtrh: Descriptor handle.
|
|
* @cksum_bits: Specifies which checksums are to be offloaded: IPv4,
|
|
* and/or TCP and/or UDP.
|
|
*
|
|
* Ask Xframe to calculate IPv4 & transport checksums for _this_ transmit
|
|
* descriptor.
|
|
* This API is part of the preparation of the transmit descriptor for posting
|
|
* (via xge_hal_fifo_dtr_post()). The related "preparation" APIs include
|
|
* xge_hal_fifo_dtr_mss_set(), xge_hal_fifo_dtr_buffer_set_aligned(),
|
|
* and xge_hal_fifo_dtr_buffer_set().
|
|
* All these APIs fill in the fields of the fifo descriptor,
|
|
* in accordance with the Xframe specification.
|
|
*
|
|
* See also: xge_hal_fifo_dtr_reserve(),
|
|
* xge_hal_fifo_dtr_post(), XGE_HAL_TXD_TX_CKO_IPV4_EN,
|
|
* XGE_HAL_TXD_TX_CKO_TCP_EN.
|
|
* Usage: See ex_xmit{}.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits)
|
|
{
|
|
xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
|
|
|
|
txdp->control_2 |= cksum_bits;
|
|
}
|
|
|
|
|
|
/**
|
|
* xge_hal_fifo_dtr_vlan_set - Set VLAN tag.
|
|
* @dtrh: Descriptor handle.
|
|
* @vlan_tag: 16bit VLAN tag.
|
|
*
|
|
* Insert VLAN tag into specified transmit descriptor.
|
|
* The actual insertion of the tag into outgoing frame is done by the hardware.
|
|
* See also: xge_hal_fifo_dtr_buffer_set(), xge_hal_fifo_dtr_mss_set().
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO void
|
|
xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag)
|
|
{
|
|
xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
|
|
|
|
txdp->control_2 |= XGE_HAL_TXD_VLAN_ENABLE;
|
|
txdp->control_2 |= XGE_HAL_TXD_VLAN_TAG(vlan_tag);
|
|
}
|
|
|
|
/**
|
|
* xge_hal_fifo_is_next_dtr_completed - Checks if the next dtr is completed
|
|
* @channelh: Channel handle.
|
|
*/
|
|
__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e
|
|
xge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh)
|
|
{
|
|
xge_hal_fifo_txd_t *txdp;
|
|
xge_hal_dtr_h dtrh;
|
|
|
|
__hal_channel_dtr_try_complete(channelh, &dtrh);
|
|
txdp = (xge_hal_fifo_txd_t *)dtrh;
|
|
if (txdp == NULL) {
|
|
return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
|
|
}
|
|
|
|
/* check whether host owns it */
|
|
if ( !(txdp->control_1 & XGE_HAL_TXD_LIST_OWN_XENA) ) {
|
|
xge_assert(txdp->host_control!=0);
|
|
return XGE_HAL_OK;
|
|
}
|
|
|
|
/* no more completions */
|
|
return XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS;
|
|
}
|