Jung-uk Kim cd45fec044 Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta ... CPUs. These CPUs need explicit MSR configuration to expose ceratin CPU capabilities (e.g., CMPXCHG8B) to work around compatibility issues with ancient software. Unfortunately, Rise mP6 does not set the CX8 bit in CPUID and there is no MSR to expose the feature although all mP6 processors are capable of CMPXCHG8B according to datasheets I found from the Net. Clean up and simplify VIA PadLock detection while I am in the neighborhood.		2011-03-26 02:02:07 +00:00
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acpica	sysctl(9) cleanup checkpoint: amd64 GENERIC builds cleanly.	2011-01-12 19:54:19 +00:00
amd64	Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta	2011-03-26 02:02:07 +00:00
compile
conf	For now remove options FLOWTABLE from the remaining GENERIC kernel	2011-03-19 15:50:34 +00:00
ia32	Clear the padding when returning context to the usermode, for	2011-02-05 15:10:27 +00:00
include	- Merge changes to the base system to support OFED. These include	2011-03-21 09:40:01 +00:00
linux32	Enable shared page use for amd64/linux32 and i386/linux binaries.	2011-03-13 14:58:02 +00:00
pci	number of cleanups in i386 and amd64 pci md code	2009-09-24 07:11:23 +00:00
Makefile	Adjustments to make a tags file a bit more suitable to amd64.	2008-12-01 14:15:10 +00:00