fd8516cc05
This adds clocks support for the aw_ccung on the A31 SoC. Newer DTS files require this. All the clocks except two CSI are defined and exported on the clock domain.
251 lines
7.7 KiB
C
251 lines
7.7 KiB
C
/*-
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* Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __CCU_A31_H__
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#define __CCU_A31_H__
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#define A31_RST_USB_PHY0 0
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#define A31_RST_USB_PHY1 1
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#define A31_RST_USB_PHY2 2
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#define A31_RST_AHB1_MIPI_DSI 3
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#define A31_RST_AHB1_SS 4
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#define A31_RST_AHB1_DMA 5
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#define A31_RST_AHB1_MMC0 6
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#define A31_RST_AHB1_MMC1 7
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#define A31_RST_AHB1_MMC2 8
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#define A31_RST_AHB1_MMC3 9
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#define A31_RST_AHB1_NAND1 10
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#define A31_RST_AHB1_NAND0 11
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#define A31_RST_AHB1_SDRAM 12
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#define A31_RST_AHB1_EMAC 13
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#define A31_RST_AHB1_TS 14
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#define A31_RST_AHB1_HSTIMER 15
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#define A31_RST_AHB1_SPI0 16
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#define A31_RST_AHB1_SPI1 17
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#define A31_RST_AHB1_SPI2 18
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#define A31_RST_AHB1_SPI3 19
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#define A31_RST_AHB1_OTG 20
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#define A31_RST_AHB1_EHCI0 21
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#define A31_RST_AHB1_EHCI1 22
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#define A31_RST_AHB1_OHCI0 23
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#define A31_RST_AHB1_OHCI1 24
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#define A31_RST_AHB1_OHCI2 25
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#define A31_RST_AHB1_VE 26
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#define A31_RST_AHB1_LCD0 27
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#define A31_RST_AHB1_LCD1 28
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#define A31_RST_AHB1_CSI 29
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#define A31_RST_AHB1_HDMI 30
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#define A31_RST_AHB1_BE0 31
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#define A31_RST_AHB1_BE1 32
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#define A31_RST_AHB1_FE0 33
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#define A31_RST_AHB1_FE1 34
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#define A31_RST_AHB1_MP 35
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#define A31_RST_AHB1_GPU 36
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#define A31_RST_AHB1_DEU0 37
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#define A31_RST_AHB1_DEU1 38
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#define A31_RST_AHB1_DRC0 39
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#define A31_RST_AHB1_DRC1 40
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#define A31_RST_AHB1_LVDS 41
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#define A31_RST_APB1_CODEC 42
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#define A31_RST_APB1_SPDIF 43
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#define A31_RST_APB1_DIGITAL_MIC 44
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#define A31_RST_APB1_DAUDIO0 45
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#define A31_RST_APB1_DAUDIO1 46
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#define A31_RST_APB2_I2C0 47
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#define A31_RST_APB2_I2C1 48
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#define A31_RST_APB2_I2C2 49
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#define A31_RST_APB2_I2C3 50
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#define A31_RST_APB2_UART0 51
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#define A31_RST_APB2_UART1 52
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#define A31_RST_APB2_UART2 53
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#define A31_RST_APB2_UART3 54
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#define A31_RST_APB2_UART4 55
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#define A31_RST_APB2_UART5 56
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#define A31_CLK_PLL_CPU 0
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#define A31_CLK_PLL_AUDIO_BASE 1
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#define A31_CLK_PLL_AUDIO 2
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#define A31_CLK_PLL_AUDIO_2X 3
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#define A31_CLK_PLL_AUDIO_4X 4
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#define A31_CLK_PLL_AUDIO_8X 5
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#define A31_CLK_PLL_VIDEO0 6
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#define A31_CLK_PLL_VIDEO0_2X 7
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#define A31_CLK_PLL_VE 8
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#define A31_CLK_PLL_DDR 9
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#define A31_CLK_PLL_PERIPH 10
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#define A31_CLK_PLL_PERIPH_2X 11
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#define A31_CLK_PLL_VIDEO1 12
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#define A31_CLK_PLL_VIDEO1_2X 13
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#define A31_CLK_PLL_GPU 14
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#define A31_CLK_PLL_MIPI 15
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#define A31_CLK_PLL9 16
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#define A31_CLK_PLL10 17
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#define A31_CLK_CPU 18
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#define A31_CLK_AXI 19
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#define A31_CLK_AHB1 20
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#define A31_CLK_APB1 21
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#define A31_CLK_APB2 22
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#define A31_CLK_AHB1_MIPIDSI 23
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#define A31_CLK_AHB1_SS 24
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#define A31_CLK_AHB1_DMA 25
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#define A31_CLK_AHB1_MMC0 26
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#define A31_CLK_AHB1_MMC1 27
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#define A31_CLK_AHB1_MMC2 28
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#define A31_CLK_AHB1_MMC3 29
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#define A31_CLK_AHB1_NAND1 30
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#define A31_CLK_AHB1_NAND0 31
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#define A31_CLK_AHB1_SDRAM 32
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#define A31_CLK_AHB1_EMAC 33
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#define A31_CLK_AHB1_TS 34
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#define A31_CLK_AHB1_HSTIMER 35
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#define A31_CLK_AHB1_SPI0 36
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#define A31_CLK_AHB1_SPI1 37
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#define A31_CLK_AHB1_SPI2 38
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#define A31_CLK_AHB1_SPI3 39
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#define A31_CLK_AHB1_OTG 40
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#define A31_CLK_AHB1_EHCI0 41
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#define A31_CLK_AHB1_EHCI1 42
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#define A31_CLK_AHB1_OHCI0 43
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#define A31_CLK_AHB1_OHCI1 44
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#define A31_CLK_AHB1_OHCI2 45
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#define A31_CLK_AHB1_VE 46
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#define A31_CLK_AHB1_LCD0 47
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#define A31_CLK_AHB1_LCD1 48
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#define A31_CLK_AHB1_CSI 49
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#define A31_CLK_AHB1_HDMI 50
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#define A31_CLK_AHB1_BE0 51
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#define A31_CLK_AHB1_BE1 52
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#define A31_CLK_AHB1_FE0 53
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#define A31_CLK_AHB1_FE1 54
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#define A31_CLK_AHB1_MP 55
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#define A31_CLK_AHB1_GPU 56
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#define A31_CLK_AHB1_DEU0 57
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#define A31_CLK_AHB1_DEU1 58
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#define A31_CLK_AHB1_DRC0 59
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#define A31_CLK_AHB1_DRC1 60
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#define A31_CLK_APB1_CODEC 61
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#define A31_CLK_APB1_SPDIF 62
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#define A31_CLK_APB1_DIGITAL_MIC 63
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#define A31_CLK_APB1_PIO 64
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#define A31_CLK_APB1_DAUDIO0 65
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#define A31_CLK_APB1_DAUDIO1 66
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#define A31_CLK_APB2_I2C0 67
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#define A31_CLK_APB2_I2C1 68
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#define A31_CLK_APB2_I2C2 69
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#define A31_CLK_APB2_I2C3 70
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#define A31_CLK_APB2_UART0 71
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#define A31_CLK_APB2_UART1 72
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#define A31_CLK_APB2_UART2 73
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#define A31_CLK_APB2_UART3 74
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#define A31_CLK_APB2_UART4 75
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#define A31_CLK_APB2_UART5 76
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#define A31_CLK_NAND0 77
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#define A31_CLK_NAND1 78
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#define A31_CLK_MMC0 79
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#define A31_CLK_MMC0_SAMPLE 80
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#define A31_CLK_MMC0_OUTPUT 81
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#define A31_CLK_MMC1 82
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#define A31_CLK_MMC1_SAMPLE 83
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#define A31_CLK_MMC1_OUTPUT 84
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#define A31_CLK_MMC2 85
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#define A31_CLK_MMC2_SAMPLE 86
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#define A31_CLK_MMC2_OUTPUT 87
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#define A31_CLK_MMC3 88
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#define A31_CLK_MMC3_SAMPLE 89
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#define A31_CLK_MMC3_OUTPUT 90
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#define A31_CLK_TS 91
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#define A31_CLK_SS 92
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#define A31_CLK_SPI0 93
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#define A31_CLK_SPI1 94
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#define A31_CLK_SPI2 95
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#define A31_CLK_SPI3 96
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#define A31_CLK_DAUDIO0 97
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#define A31_CLK_DAUDIO1 98
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#define A31_CLK_SPDIF 99
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#define A31_CLK_USB_PHY0 100
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#define A31_CLK_USB_PHY1 101
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#define A31_CLK_USB_PHY2 102
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#define A31_CLK_USB_OHCI0 103
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#define A31_CLK_USB_OHCI1 104
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#define A31_CLK_USB_OHCI2 105
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#define A31_CLK_MDFS 107
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#define A31_CLK_SDRAM0 108
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#define A31_CLK_SDRAM1 109
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#define A31_CLK_DRAM_VE 110
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#define A31_CLK_DRAM_CSI_ISP 111
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#define A31_CLK_DRAM_TS 112
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#define A31_CLK_DRAM_DRC0 113
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#define A31_CLK_DRAM_DRC1 114
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#define A31_CLK_DRAM_DEU0 115
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#define A31_CLK_DRAM_DEU1 116
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#define A31_CLK_DRAM_FE0 117
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#define A31_CLK_DRAM_FE1 118
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#define A31_CLK_DRAM_BE0 119
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#define A31_CLK_DRAM_BE1 120
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#define A31_CLK_DRAM_MP 121
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#define A31_CLK_BE0 122
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#define A31_CLK_BE1 123
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#define A31_CLK_FE0 124
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#define A31_CLK_FE1 125
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#define A31_CLK_MP 126
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#define A31_CLK_LCD0_CH0 127
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#define A31_CLK_LCD1_CH0 128
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#define A31_CLK_LCD0_CH1 129
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#define A31_CLK_LCD1_CH1 130
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#define A31_CLK_CSI0_SCLK 131
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#define A31_CLK_CSI0_MCLK 132
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#define A31_CLK_CSI1_MCLK 133
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#define A31_CLK_VE 134
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#define A31_CLK_CODEC 135
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#define A31_CLK_AVS 136
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#define A31_CLK_DIGITAL_MIC 137
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#define A31_CLK_HDMI 138
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#define A31_CLK_HDMI_DDC 139
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#define A31_CLK_PS 140
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#define A31_CLK_MBUS0 141
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#define A31_CLK_MBUS1 142
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#define A31_CLK_MIPI_DSI 143
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#define A31_CLK_MIPI_DSI_DPHY 144
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#define A31_CLK_MIPI_CSI_DPHY 145
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#define A31_CLK_IEP_DRC0 146
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#define A31_CLK_IEP_DRC1 147
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#define A31_CLK_IEP_DEU0 148
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#define A31_CLK_IEP_DEU1 149
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#define A31_CLK_GPU_CORE 150
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#define A31_CLK_GPU_MEMORY 151
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#define A31_CLK_GPU_HYD 152
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#define A31_CLK_ATS 153
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#define A31_CLK_TRACE 154
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#define A31_CLK_OUT_A 155
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#define A31_CLK_OUT_B 156
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#define A31_CLK_OUT_C 157
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void ccu_a31_register_clocks(struct aw_ccung_softc *sc);
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#endif /* __CCU_A31 H__ */
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