cfc8861b06
- Put all clock and control unit driver in BUS_PASS_RESOURCE except for the DE2 CCU as it needs the main CCU to be available. - Use BUS_PASS_CPU for a20_cpu_cfg as it makes more sense. - For aw_syscon use SCHEDULER pass as we need it early for drivers that attach in BUS_PASS_SUPPORTDEV - For the rest we can use BUS_PASS_SUPPORTDEV
572 lines
15 KiB
C
572 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <arm/allwinner/clkng/aw_ccung.h>
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#include <dt-bindings/clock/sun5i-ccu.h>
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#include <dt-bindings/reset/sun5i-ccu.h>
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/* Non-exported clocks */
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#define CLK_PLL_CORE 2
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#define CLK_PLL_AUDIO_BASE 3
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#define CLK_PLL_AUDIO 4
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#define CLK_PLL_AUDIO_2X 5
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#define CLK_PLL_AUDIO_4X 6
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#define CLK_PLL_AUDIO_8X 7
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#define CLK_PLL_VIDEO0 8
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#define CLK_PLL_VE 10
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#define CLK_PLL_DDR_BASE 11
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#define CLK_PLL_DDR 12
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#define CLK_PLL_DDR_OTHER 13
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#define CLK_PLL_PERIPH 14
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#define CLK_PLL_VIDEO1 15
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#define CLK_AXI 18
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#define CLK_AHB 19
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#define CLK_APB0 20
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#define CLK_APB1 21
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#define CLK_DRAM_AXI 22
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#define CLK_TCON_CH1_SCLK 91
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#define CLK_MBUS 99
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static struct aw_ccung_reset a13_ccu_resets[] = {
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CCU_RESET(RST_USB_PHY0, 0xcc, 0)
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CCU_RESET(RST_USB_PHY1, 0xcc, 1)
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CCU_RESET(RST_GPS, 0xd0, 30)
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CCU_RESET(RST_DE_BE, 0x104, 30)
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CCU_RESET(RST_DE_FE, 0x10c, 30)
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CCU_RESET(RST_TVE, 0x118, 29)
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CCU_RESET(RST_LCD, 0x118, 30)
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CCU_RESET(RST_CSI, 0x134, 30)
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CCU_RESET(RST_VE, 0x13c, 0)
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CCU_RESET(RST_GPU, 0x154, 30)
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CCU_RESET(RST_IEP, 0x160, 30)
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};
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static struct aw_ccung_gate a13_ccu_gates[] = {
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CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0)
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CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
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CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
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CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
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CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
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CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
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CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
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CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
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CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
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CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
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CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10)
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CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13)
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CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14)
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CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20)
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CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21)
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CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22)
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CCU_GATE(CLK_AHB_GPS, "ahb-gps", "ahb", 0x60, 26)
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CCU_GATE(CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 0x60, 28)
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CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0)
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CCU_GATE(CLK_AHB_LCD, "ahb-lcd", "ahb", 0x64, 4)
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CCU_GATE(CLK_AHB_CSI, "ahb-csi", "ahb", 0x64, 8)
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CCU_GATE(CLK_AHB_DE_BE, "ahb-de-be", "ahb", 0x64, 12)
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CCU_GATE(CLK_AHB_DE_FE, "ahb-de-fe", "ahb", 0x64, 14)
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CCU_GATE(CLK_AHB_IEP, "ahb-iep", "ahb", 0x64, 19)
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CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20)
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CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0)
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CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x68, 5)
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CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x68, 6)
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CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0)
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CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1", 0x6c, 1)
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CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1", 0x6c, 2)
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CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1", 0x6c, 17)
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CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1", 0x6c, 19)
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CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll-ddr", 0x100, 0)
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CCU_GATE(CLK_DRAM_CSI, "dram-csi", "pll-ddr", 0x100, 1)
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CCU_GATE(CLK_DRAM_DE_FE, "dram-de-fe", "pll-ddr", 0x100, 25)
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CCU_GATE(CLK_DRAM_DE_BE, "dram-de-be", "pll-ddr", 0x100, 26)
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CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll-ddr", 0x100, 29)
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CCU_GATE(CLK_DRAM_IEP, "dram-iep", "pll-ddr", 0x100, 31)
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CCU_GATE(CLK_CODEC, "codec", "pll-audio", 0x140, 31)
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CCU_GATE(CLK_AVS, "avs", "hosc", 0x144, 31)
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};
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static const char *pll_parents[] = {"hosc"};
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static struct aw_clk_nkmp_def pll_core = {
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.clkdef = {
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.id = CLK_PLL_CORE,
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.name = "pll-core",
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.parent_names = pll_parents,
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.parent_cnt = nitems(pll_parents),
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},
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.offset = 0x00,
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.n = {.shift = 8, .width = 5},
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.k = {.shift = 4, .width = 2},
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.m = {.shift = 0, .width = 2},
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.p = {.shift = 16, .width = 2},
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.gate_shift = 31,
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.flags = AW_CLK_HAS_GATE,
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};
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/*
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* We only implement pll-audio for now
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* For pll-audio-2/4/8 x we need a way to change the frequency
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* of the parent clocks
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*/
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static struct aw_clk_nkmp_def pll_audio = {
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.clkdef = {
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.id = CLK_PLL_AUDIO,
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.name = "pll-audio",
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.parent_names = pll_parents,
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.parent_cnt = nitems(pll_parents),
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},
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.offset = 0x08,
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.n = {.shift = 8, .width = 7},
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.k = {.value = 1, .flags = AW_CLK_FACTOR_FIXED},
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.m = {.shift = 0, .width = 5},
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.p = {.shift = 26, .width = 4},
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.gate_shift = 31,
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.flags = AW_CLK_HAS_GATE,
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};
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/* Missing PLL3-Video */
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/* Missing PLL4-VE */
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static struct aw_clk_nkmp_def pll_ddr_base = {
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.clkdef = {
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.id = CLK_PLL_DDR_BASE,
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.name = "pll-ddr-base",
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.parent_names = pll_parents,
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.parent_cnt = nitems(pll_parents),
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},
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.offset = 0x20,
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.n = {.shift = 8, .width = 5},
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.k = {.shift = 4, .width = 2},
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.m = {.value = 1, .flags = AW_CLK_FACTOR_FIXED},
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.p = {.value = 1, .flags = AW_CLK_FACTOR_FIXED},
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.gate_shift = 31,
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.flags = AW_CLK_HAS_GATE,
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};
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static const char *pll_ddr_parents[] = {"pll-ddr-base"};
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static struct clk_div_def pll_ddr = {
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.clkdef = {
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.id = CLK_PLL_DDR,
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.name = "pll-ddr",
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.parent_names = pll_ddr_parents,
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.parent_cnt = nitems(pll_ddr_parents),
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},
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.offset = 0x20,
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.i_shift = 0,
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.i_width = 2,
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};
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static const char *pll_ddr_other_parents[] = {"pll-ddr-base"};
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static struct clk_div_def pll_ddr_other = {
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.clkdef = {
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.id = CLK_PLL_DDR_OTHER,
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.name = "pll-ddr-other",
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.parent_names = pll_ddr_other_parents,
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.parent_cnt = nitems(pll_ddr_other_parents),
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},
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.offset = 0x20,
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.i_shift = 16,
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.i_width = 2,
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};
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static struct aw_clk_nkmp_def pll_periph = {
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.clkdef = {
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.id = CLK_PLL_PERIPH,
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.name = "pll-periph",
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.parent_names = pll_parents,
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.parent_cnt = nitems(pll_parents),
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},
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.offset = 0x28,
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.n = {.shift = 8, .width = 5},
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.k = {.shift = 4, .width = 2},
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.m = {.shift = 0, .width = 2},
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.p = {.value = 2, .flags = AW_CLK_FACTOR_FIXED},
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.gate_shift = 31,
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.flags = AW_CLK_HAS_GATE,
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};
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/* Missing PLL7-VIDEO1 */
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static const char *cpu_parents[] = {"osc32k", "hosc", "pll-core", "pll-periph"};
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static struct aw_clk_prediv_mux_def cpu_clk = {
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.clkdef = {
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.id = CLK_CPU,
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.name = "cpu",
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.parent_names = cpu_parents,
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.parent_cnt = nitems(cpu_parents),
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},
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.offset = 0x54,
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.mux_shift = 16, .mux_width = 2,
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.prediv = {
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.value = 6,
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.flags = AW_CLK_FACTOR_FIXED,
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.cond_shift = 16,
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.cond_width = 2,
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.cond_value = 3,
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},
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};
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static const char *axi_parents[] = {"cpu"};
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static struct clk_div_def axi_clk = {
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.clkdef = {
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.id = CLK_AXI,
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.name = "axi",
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.parent_names = axi_parents,
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.parent_cnt = nitems(axi_parents),
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},
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.offset = 0x50,
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.i_shift = 0, .i_width = 2,
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};
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static const char *ahb_parents[] = {"axi", "cpu", "pll-periph"};
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static struct aw_clk_prediv_mux_def ahb_clk = {
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.clkdef = {
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.id = CLK_AHB,
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.name = "ahb",
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.parent_names = ahb_parents,
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.parent_cnt = nitems(ahb_parents),
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},
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.offset = 0x54,
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.mux_shift = 6,
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.mux_width = 2,
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.div = {
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.shift = 4,
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.width = 2,
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.flags = AW_CLK_FACTOR_POWER_OF_TWO
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},
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.prediv = {
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.value = 2,
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.flags = AW_CLK_FACTOR_FIXED,
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.cond_shift = 6,
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.cond_width = 2,
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.cond_value = 2,
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},
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};
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static const char *apb0_parents[] = {"ahb"};
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static struct clk_div_table apb0_div_table[] = {
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{ .value = 0, .divider = 2, },
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{ .value = 1, .divider = 2, },
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{ .value = 2, .divider = 4, },
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{ .value = 3, .divider = 8, },
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{ },
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};
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static struct clk_div_def apb0_clk = {
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.clkdef = {
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.id = CLK_APB0,
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.name = "apb0",
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.parent_names = apb0_parents,
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.parent_cnt = nitems(apb0_parents),
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},
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.offset = 0x54,
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.i_shift = 8, .i_width = 2,
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.div_flags = CLK_DIV_WITH_TABLE,
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.div_table = apb0_div_table,
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};
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static const char *apb1_parents[] = {"hosc", "pll-periph", "osc32k"};
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static struct aw_clk_nm_def apb1_clk = {
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.clkdef = {
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.id = CLK_APB1,
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.name = "apb1",
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.parent_names = apb1_parents,
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.parent_cnt = nitems(apb1_parents),
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},
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.offset = 0x58,
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.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
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.m = {.shift = 0, .width = 5},
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.mux_shift = 24,
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.mux_width = 2,
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.flags = AW_CLK_HAS_MUX,
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};
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static const char *mod_parents[] = {"hosc", "pll-periph", "pll-ddr-other"};
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static struct aw_clk_nm_def nand_clk = {
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.clkdef = {
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.id = CLK_NAND,
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.name = "nand",
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.parent_names = mod_parents,
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.parent_cnt = nitems(mod_parents),
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},
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.offset = 0x80,
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.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
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.m = {.shift = 0, .width = 4},
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.mux_shift = 24,
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.mux_width = 2,
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.gate_shift = 31,
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.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
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};
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static struct aw_clk_nm_def mmc0_clk = {
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.clkdef = {
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.id = CLK_MMC0,
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.name = "mmc0",
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.parent_names = mod_parents,
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.parent_cnt = nitems(mod_parents),
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},
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.offset = 0x88,
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.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
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.m = {.shift = 0, .width = 4},
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.mux_shift = 24,
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.mux_width = 2,
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.gate_shift = 31,
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.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
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};
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static struct aw_clk_nm_def mmc1_clk = {
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.clkdef = {
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.id = CLK_MMC1,
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.name = "mmc1",
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.parent_names = mod_parents,
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.parent_cnt = nitems(mod_parents),
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},
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.offset = 0x8C,
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.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
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.m = {.shift = 0, .width = 4},
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.mux_shift = 24,
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.mux_width = 2,
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.gate_shift = 31,
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.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
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};
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static struct aw_clk_nm_def mmc2_clk = {
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.clkdef = {
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.id = CLK_MMC2,
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.name = "mmc2",
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.parent_names = mod_parents,
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.parent_cnt = nitems(mod_parents),
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},
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.offset = 0x90,
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.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
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.m = {.shift = 0, .width = 4},
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.mux_shift = 24,
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.mux_width = 2,
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.gate_shift = 31,
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.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
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};
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static struct aw_clk_nm_def ss_clk = {
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.clkdef = {
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.id = CLK_SS,
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.name = "ss",
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.parent_names = mod_parents,
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.parent_cnt = nitems(mod_parents),
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},
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.offset = 0x9C,
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.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
|
|
.m = {.shift = 0, .width = 4},
|
|
.mux_shift = 24,
|
|
.mux_width = 2,
|
|
.gate_shift = 31,
|
|
.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
|
|
};
|
|
|
|
static struct aw_clk_nm_def spi0_clk = {
|
|
.clkdef = {
|
|
.id = CLK_SPI0,
|
|
.name = "spi0",
|
|
.parent_names = mod_parents,
|
|
.parent_cnt = nitems(mod_parents),
|
|
},
|
|
.offset = 0xA0,
|
|
.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
|
|
.m = {.shift = 0, .width = 4},
|
|
.mux_shift = 24,
|
|
.mux_width = 2,
|
|
.gate_shift = 31,
|
|
.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
|
|
};
|
|
|
|
static struct aw_clk_nm_def spi1_clk = {
|
|
.clkdef = {
|
|
.id = CLK_SPI1,
|
|
.name = "spi1",
|
|
.parent_names = mod_parents,
|
|
.parent_cnt = nitems(mod_parents),
|
|
},
|
|
.offset = 0xA4,
|
|
.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
|
|
.m = {.shift = 0, .width = 4},
|
|
.mux_shift = 24,
|
|
.mux_width = 2,
|
|
.gate_shift = 31,
|
|
.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
|
|
};
|
|
|
|
static struct aw_clk_nm_def spi2_clk = {
|
|
.clkdef = {
|
|
.id = CLK_SPI2,
|
|
.name = "spi2",
|
|
.parent_names = mod_parents,
|
|
.parent_cnt = nitems(mod_parents),
|
|
},
|
|
.offset = 0xA8,
|
|
.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
|
|
.m = {.shift = 0, .width = 4},
|
|
.mux_shift = 24,
|
|
.mux_width = 2,
|
|
.gate_shift = 31,
|
|
.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
|
|
};
|
|
|
|
static struct aw_clk_nm_def ir_clk = {
|
|
.clkdef = {
|
|
.id = CLK_IR,
|
|
.name = "ir",
|
|
.parent_names = mod_parents,
|
|
.parent_cnt = nitems(mod_parents),
|
|
},
|
|
.offset = 0xB0,
|
|
.n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
|
|
.m = {.shift = 0, .width = 4},
|
|
.mux_shift = 24,
|
|
.mux_width = 2,
|
|
.gate_shift = 31,
|
|
.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
|
|
};
|
|
|
|
/* Missing DE-BE clock */
|
|
/* Missing DE-FE clock */
|
|
/* Missing LCD CH1 clock */
|
|
/* Missing CSI clock */
|
|
/* Missing VE clock */
|
|
|
|
|
|
/* Clocks list */
|
|
static struct aw_ccung_clk a13_ccu_clks[] = {
|
|
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_core},
|
|
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio},
|
|
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_base},
|
|
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph},
|
|
{ .type = AW_CLK_NM, .clk.nm = &apb1_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &nand_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &ss_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &spi0_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &spi1_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &spi2_clk},
|
|
{ .type = AW_CLK_NM, .clk.nm = &ir_clk},
|
|
{ .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &cpu_clk},
|
|
{ .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb_clk},
|
|
{ .type = AW_CLK_DIV, .clk.div = &pll_ddr},
|
|
{ .type = AW_CLK_DIV, .clk.div = &pll_ddr_other},
|
|
{ .type = AW_CLK_DIV, .clk.div = &axi_clk},
|
|
{ .type = AW_CLK_DIV, .clk.div = &apb0_clk},
|
|
};
|
|
|
|
static int
|
|
ccu_a13_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_is_compatible(dev, "allwinner,sun5i-a13-ccu"))
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Allwinner A13 Clock Control Unit NG");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
ccu_a13_attach(device_t dev)
|
|
{
|
|
struct aw_ccung_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sc->resets = a13_ccu_resets;
|
|
sc->nresets = nitems(a13_ccu_resets);
|
|
sc->gates = a13_ccu_gates;
|
|
sc->ngates = nitems(a13_ccu_gates);
|
|
sc->clks = a13_ccu_clks;
|
|
sc->nclks = nitems(a13_ccu_clks);
|
|
|
|
return (aw_ccung_attach(dev));
|
|
}
|
|
|
|
static device_method_t ccu_a13ng_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, ccu_a13_probe),
|
|
DEVMETHOD(device_attach, ccu_a13_attach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t ccu_a13ng_devclass;
|
|
|
|
DEFINE_CLASS_1(ccu_a13ng, ccu_a13ng_driver, ccu_a13ng_methods,
|
|
sizeof(struct aw_ccung_softc), aw_ccung_driver);
|
|
|
|
EARLY_DRIVER_MODULE(ccu_a13ng, simplebus, ccu_a13ng_driver,
|
|
ccu_a13ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
|