a0fd233964
It can be compiled into the kernel with "device imx_spi" or loaded as a module, which is also named "imx_spi".
665 lines
17 KiB
C
665 lines
17 KiB
C
/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-2-Clause AND BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by Oleksandr Rybalko
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Clock Controller Module (CCM)
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <arm/freescale/imx/imx51_ccmvar.h>
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#include <arm/freescale/imx/imx51_ccmreg.h>
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#include <arm/freescale/imx/imx51_dpllreg.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#include <arm/freescale/imx/imx_machdep.h>
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#define IMXCCMDEBUG
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#undef IMXCCMDEBUG
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#ifndef IMX51_OSC_FREQ
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#define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
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#endif
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#ifndef IMX51_CKIL_FREQ
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#define IMX51_CKIL_FREQ 32768
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#endif
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/*
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* The fdt data does not provide reg properties describing the DPLL register
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* blocks we need to access, presumably because the needed addresses are
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* hard-coded within the linux driver. That leaves us with no choice but to do
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* the same thing, if we want to run with vendor-supplied fdt data. So here we
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* have tables of the physical addresses we need for each soc, and we'll use
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* bus_space_map() at attach() time to get access to them.
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*/
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static uint32_t imx51_dpll_addrs[IMX51_N_DPLLS] = {
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0x83f80000, /* DPLL1 */
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0x83f84000, /* DPLL2 */
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0x83f88000, /* DPLL3 */
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};
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static uint32_t imx53_dpll_addrs[IMX51_N_DPLLS] = {
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0x63f80000, /* DPLL1 */
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0x63f84000, /* DPLL2 */
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0x63f88000, /* DPLL3 */
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};
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#define DPLL_REGS_SZ (16 * 1024)
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struct imxccm_softc {
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device_t sc_dev;
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struct resource *ccmregs;
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u_int64_t pll_freq[IMX51_N_DPLLS];
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bus_space_tag_t pllbst;
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bus_space_handle_t pllbsh[IMX51_N_DPLLS];
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};
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struct imxccm_softc *ccm_softc = NULL;
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static uint64_t imx51_get_pll_freq(u_int);
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static int imxccm_match(device_t);
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static int imxccm_attach(device_t);
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static device_method_t imxccm_methods[] = {
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DEVMETHOD(device_probe, imxccm_match),
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DEVMETHOD(device_attach, imxccm_attach),
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DEVMETHOD_END
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};
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static driver_t imxccm_driver = {
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"imxccm",
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imxccm_methods,
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sizeof(struct imxccm_softc),
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};
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static devclass_t imxccm_devclass;
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EARLY_DRIVER_MODULE(imxccm, simplebus, imxccm_driver, imxccm_devclass, 0, 0,
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BUS_PASS_CPU);
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static inline uint32_t
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pll_read_4(struct imxccm_softc *sc, int pll, int reg)
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{
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return (bus_space_read_4(sc->pllbst, sc->pllbsh[pll - 1], reg));
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}
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static inline uint32_t
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ccm_read_4(struct imxccm_softc *sc, int reg)
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{
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return (bus_read_4(sc->ccmregs, reg));
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}
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static inline void
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ccm_write_4(struct imxccm_softc *sc, int reg, uint32_t val)
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{
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bus_write_4(sc->ccmregs, reg, val);
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}
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static int
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imxccm_match(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,imx51-ccm") &&
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!ofw_bus_is_compatible(dev, "fsl,imx53-ccm"))
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return (ENXIO);
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device_set_desc(dev, "Freescale Clock Control Module");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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imxccm_attach(device_t dev)
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{
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struct imxccm_softc *sc;
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int idx;
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u_int soc;
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uint32_t *pll_addrs;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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switch ((soc = imx_soc_type())) {
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case IMXSOC_51:
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pll_addrs = imx51_dpll_addrs;
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break;
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case IMXSOC_53:
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pll_addrs = imx53_dpll_addrs;
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break;
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default:
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device_printf(dev, "No support for SoC type 0x%08x\n", soc);
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goto noclocks;
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}
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idx = 0;
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sc->ccmregs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &idx,
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RF_ACTIVE);
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if (sc->ccmregs == NULL) {
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device_printf(dev, "could not allocate resources\n");
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goto noclocks;
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}
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sc->pllbst = fdtbus_bs_tag;
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for (idx = 0; idx < IMX51_N_DPLLS; ++idx) {
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if (bus_space_map(sc->pllbst, pll_addrs[idx], DPLL_REGS_SZ, 0,
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&sc->pllbsh[idx]) != 0) {
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device_printf(dev, "Cannot map DPLL registers\n");
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goto noclocks;
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}
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}
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ccm_softc = sc;
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imx51_get_pll_freq(1);
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imx51_get_pll_freq(2);
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imx51_get_pll_freq(3);
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device_printf(dev, "PLL1=%lluMHz, PLL2=%lluMHz, PLL3=%lluMHz\n",
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sc->pll_freq[0] / 1000000,
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sc->pll_freq[1] / 1000000,
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sc->pll_freq[2] / 1000000);
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device_printf(dev, "CPU clock=%d, UART clock=%d\n",
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imx51_get_clock(IMX51CLK_ARM_ROOT),
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imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
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device_printf(dev,
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"mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n",
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imx51_get_clock(IMX51CLK_MAIN_BUS_CLK),
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imx51_get_clock(IMX51CLK_AHB_CLK_ROOT),
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imx51_get_clock(IMX51CLK_IPG_CLK_ROOT),
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imx51_get_clock(IMX51CLK_PERCLK_ROOT));
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return (0);
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noclocks:
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panic("Cannot continue without clock support");
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}
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u_int
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imx51_get_clock(enum imx51_clock clk)
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{
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u_int freq;
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u_int sel;
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uint32_t cacrr; /* ARM clock root register */
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uint32_t ccsr;
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uint32_t cscdr1;
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uint32_t cscmr1;
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uint32_t cbcdr;
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uint32_t cbcmr;
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uint32_t cdcr;
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if (ccm_softc == NULL)
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return (0);
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switch (clk) {
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case IMX51CLK_PLL1:
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case IMX51CLK_PLL2:
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case IMX51CLK_PLL3:
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return ccm_softc->pll_freq[clk-IMX51CLK_PLL1];
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case IMX51CLK_PLL1SW:
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ccsr = ccm_read_4(ccm_softc, CCMC_CCSR);
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if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
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return ccm_softc->pll_freq[1-1];
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/* step clock */
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/* FALLTHROUGH */
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case IMX51CLK_PLL1STEP:
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ccsr = ccm_read_4(ccm_softc, CCMC_CCSR);
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switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) {
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case 0:
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return imx51_get_clock(IMX51CLK_LP_APM);
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case 1:
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return 0; /* XXX PLL bypass clock */
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case 2:
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return ccm_softc->pll_freq[2-1] /
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(1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >>
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CCSR_PLL2_DIV_PODF_SHIFT));
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case 3:
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return ccm_softc->pll_freq[3-1] /
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(1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >>
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CCSR_PLL3_DIV_PODF_SHIFT));
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}
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/*NOTREACHED*/
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case IMX51CLK_PLL2SW:
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ccsr = ccm_read_4(ccm_softc, CCMC_CCSR);
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if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0)
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return imx51_get_clock(IMX51CLK_PLL2);
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return 0; /* XXX PLL2 bypass clk */
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case IMX51CLK_PLL3SW:
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ccsr = ccm_read_4(ccm_softc, CCMC_CCSR);
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if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0)
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return imx51_get_clock(IMX51CLK_PLL3);
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return 0; /* XXX PLL3 bypass clk */
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case IMX51CLK_LP_APM:
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ccsr = ccm_read_4(ccm_softc, CCMC_CCSR);
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return (ccsr & CCSR_LP_APM) ?
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imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ;
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case IMX51CLK_ARM_ROOT:
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freq = imx51_get_clock(IMX51CLK_PLL1SW);
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cacrr = ccm_read_4(ccm_softc, CCMC_CACRR);
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return freq / (cacrr + 1);
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/* ... */
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case IMX51CLK_MAIN_BUS_CLK_SRC:
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cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR);
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if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0)
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freq = imx51_get_clock(IMX51CLK_PLL2SW);
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else {
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freq = 0;
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cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR);
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switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >>
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CBCMR_PERIPH_APM_SEL_SHIFT) {
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case 0:
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freq = imx51_get_clock(IMX51CLK_PLL1SW);
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break;
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case 1:
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freq = imx51_get_clock(IMX51CLK_PLL3SW);
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break;
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case 2:
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freq = imx51_get_clock(IMX51CLK_LP_APM);
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break;
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case 3:
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/* XXX: error */
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break;
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}
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}
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return freq;
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case IMX51CLK_MAIN_BUS_CLK:
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freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
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cdcr = ccm_read_4(ccm_softc, CCMC_CDCR);
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return freq / (1 + ((cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >>
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CDCR_PERIPH_CLK_DVFS_PODF_SHIFT));
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case IMX51CLK_AHB_CLK_ROOT:
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freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
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cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR);
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return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >>
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CBCDR_AHB_PODF_SHIFT));
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case IMX51CLK_IPG_CLK_ROOT:
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freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
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cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR);
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return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >>
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CBCDR_IPG_PODF_SHIFT));
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case IMX51CLK_PERCLK_ROOT:
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cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR);
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if (cbcmr & CBCMR_PERCLK_IPG_SEL)
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return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
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if (cbcmr & CBCMR_PERCLK_LP_APM_SEL)
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freq = imx51_get_clock(IMX51CLK_LP_APM);
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else
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freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
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cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR);
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#ifdef IMXCCMDEBUG
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printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
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#endif
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freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >>
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CBCDR_PERCLK_PRED1_SHIFT);
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freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >>
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CBCDR_PERCLK_PRED2_SHIFT);
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freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >>
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CBCDR_PERCLK_PODF_SHIFT);
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return freq;
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case IMX51CLK_UART_CLK_ROOT:
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cscdr1 = ccm_read_4(ccm_softc, CCMC_CSCDR1);
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cscmr1 = ccm_read_4(ccm_softc, CCMC_CSCMR1);
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#ifdef IMXCCMDEBUG
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printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
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#endif
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sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >>
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CSCMR1_UART_CLK_SEL_SHIFT;
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freq = 0; /* shut up GCC */
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switch (sel) {
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case 0:
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case 1:
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case 2:
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freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
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break;
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case 3:
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freq = imx51_get_clock(IMX51CLK_LP_APM);
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break;
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}
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return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >>
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CSCDR1_UART_CLK_PRED_SHIFT)) /
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(1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >>
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CSCDR1_UART_CLK_PODF_SHIFT));
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case IMX51CLK_IPU_HSP_CLK_ROOT:
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freq = 0;
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cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR);
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switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >>
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CBCMR_IPU_HSP_CLK_SEL_SHIFT) {
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case 0:
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freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
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break;
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case 1:
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freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK);
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break;
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case 2:
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freq = imx51_get_clock(
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IMX51CLK_EMI_SLOW_CLK_ROOT);
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break;
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case 3:
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freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
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break;
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}
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return freq;
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default:
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device_printf(ccm_softc->sc_dev,
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"clock %d: not supported yet\n", clk);
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return 0;
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}
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}
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static uint64_t
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imx51_get_pll_freq(u_int pll_no)
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{
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uint32_t dp_ctrl;
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uint32_t dp_op;
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uint32_t dp_mfd;
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uint32_t dp_mfn;
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uint32_t mfi;
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int32_t mfn;
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uint32_t mfd;
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uint32_t pdf;
|
|
uint32_t ccr;
|
|
uint64_t freq = 0;
|
|
u_int ref = 0;
|
|
|
|
KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS, ("Wrong PLL id"));
|
|
|
|
dp_ctrl = pll_read_4(ccm_softc, pll_no, DPLL_DP_CTL);
|
|
|
|
if (dp_ctrl & DP_CTL_HFSM) {
|
|
dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_OP);
|
|
dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFD);
|
|
dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFN);
|
|
} else {
|
|
dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_OP);
|
|
dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFD);
|
|
dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFN);
|
|
}
|
|
|
|
pdf = dp_op & DP_OP_PDF_MASK;
|
|
mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT);
|
|
mfd = dp_mfd;
|
|
if (dp_mfn & 0x04000000)
|
|
/* 27bit signed value */
|
|
mfn = (uint32_t)(0xf8000000 | dp_mfn);
|
|
else
|
|
mfn = dp_mfn;
|
|
|
|
switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) {
|
|
case DP_CTL_REF_CLK_SEL_COSC:
|
|
/* Internal Oscillator */
|
|
/* TODO: get from FDT "fsl,imx-osc" */
|
|
ref = 24000000; /* IMX51_OSC_FREQ */
|
|
break;
|
|
case DP_CTL_REF_CLK_SEL_FPM:
|
|
ccr = ccm_read_4(ccm_softc, CCMC_CCR);
|
|
if (ccr & CCR_FPM_MULT)
|
|
/* TODO: get from FDT "fsl,imx-ckil" */
|
|
ref = 32768 * 1024;
|
|
else
|
|
/* TODO: get from FDT "fsl,imx-ckil" */
|
|
ref = 32768 * 512;
|
|
break;
|
|
default:
|
|
ref = 0;
|
|
}
|
|
|
|
if (dp_ctrl & DP_CTL_REF_CLK_DIV)
|
|
ref /= 2;
|
|
|
|
ref *= 4;
|
|
freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1);
|
|
freq /= pdf + 1;
|
|
|
|
if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN))
|
|
freq /= 2;
|
|
|
|
#ifdef IMXCCMDEBUG
|
|
printf("ref: %dKHz ", ref);
|
|
printf("dp_ctl: %08x ", dp_ctrl);
|
|
printf("pdf: %3d ", pdf);
|
|
printf("mfi: %3d ", mfi);
|
|
printf("mfd: %3d ", mfd);
|
|
printf("mfn: %3d ", mfn);
|
|
printf("pll: %d\n", (uint32_t)freq);
|
|
#endif
|
|
|
|
ccm_softc->pll_freq[pll_no-1] = freq;
|
|
|
|
return (freq);
|
|
}
|
|
|
|
void
|
|
imx51_clk_gating(int clk_src, int mode)
|
|
{
|
|
int field, group;
|
|
uint32_t reg;
|
|
|
|
group = CCMR_CCGR_MODULE(clk_src);
|
|
field = clk_src % CCMR_CCGR_NSOURCE;
|
|
reg = ccm_read_4(ccm_softc, CCMC_CCGR(group));
|
|
reg &= ~(0x03 << field * 2);
|
|
reg |= (mode << field * 2);
|
|
ccm_write_4(ccm_softc, CCMC_CCGR(group), reg);
|
|
}
|
|
|
|
int
|
|
imx51_get_clk_gating(int clk_src)
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = ccm_read_4(ccm_softc,
|
|
CCMC_CCGR(CCMR_CCGR_MODULE(clk_src)));
|
|
return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03);
|
|
}
|
|
|
|
/*
|
|
* Code from here down is temporary, in lieu of a SoC-independent clock API.
|
|
*/
|
|
|
|
void
|
|
imx_ccm_usb_enable(device_t dev)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/*
|
|
* Select PLL2 as the source for the USB clock.
|
|
* The default is PLL3, but U-boot changes it to PLL2.
|
|
*/
|
|
regval = ccm_read_4(ccm_softc, CCMC_CSCMR1);
|
|
regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK;
|
|
regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT;
|
|
ccm_write_4(ccm_softc, CCMC_CSCMR1, regval);
|
|
|
|
/*
|
|
* Set the USB clock pre-divider to div-by-5, post-divider to div-by-2.
|
|
*/
|
|
regval = ccm_read_4(ccm_softc, CCMC_CSCDR1);
|
|
regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK;
|
|
regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK;
|
|
regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT;
|
|
regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT;
|
|
ccm_write_4(ccm_softc, CCMC_CSCDR1, regval);
|
|
|
|
/*
|
|
* The same two clocks gates are used on imx51 and imx53.
|
|
*/
|
|
imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS);
|
|
imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS);
|
|
}
|
|
|
|
void
|
|
imx_ccm_usbphy_enable(device_t dev)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/*
|
|
* Select PLL3 as the source for the USBPHY clock. U-boot does this
|
|
* only for imx53, but the bit exists on imx51. That seems a bit
|
|
* strange, but we'll go with it until more is known.
|
|
*/
|
|
if (imx_soc_type() == IMXSOC_53) {
|
|
regval = ccm_read_4(ccm_softc, CCMC_CSCMR1);
|
|
regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT;
|
|
ccm_write_4(ccm_softc, CCMC_CSCMR1, regval);
|
|
}
|
|
|
|
/*
|
|
* For the imx51 there's just one phy gate control, enable it.
|
|
*/
|
|
if (imx_soc_type() == IMXSOC_51) {
|
|
imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* For imx53 we don't have a full set of clock defines yet, but the
|
|
* datasheet says:
|
|
* gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable)
|
|
* gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable)
|
|
*
|
|
* We should use the fdt data for the device to figure out which of
|
|
* the two we're working on, but for now just turn them both on.
|
|
*/
|
|
if (imx_soc_type() == IMXSOC_53) {
|
|
imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS);
|
|
imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS);
|
|
return;
|
|
}
|
|
}
|
|
|
|
uint32_t
|
|
imx_ccm_ecspi_hz(void)
|
|
{
|
|
|
|
return (imx51_get_clock(IMX51CLK_CSPI_CLK_ROOT));
|
|
}
|
|
|
|
uint32_t
|
|
imx_ccm_ipg_hz(void)
|
|
{
|
|
|
|
return (imx51_get_clock(IMX51CLK_IPG_CLK_ROOT));
|
|
}
|
|
|
|
uint32_t
|
|
imx_ccm_sdhci_hz(void)
|
|
{
|
|
|
|
return (imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT));
|
|
}
|
|
|
|
uint32_t
|
|
imx_ccm_perclk_hz(void)
|
|
{
|
|
|
|
return (imx51_get_clock(IMX51CLK_PERCLK_ROOT));
|
|
}
|
|
|
|
uint32_t
|
|
imx_ccm_uart_hz(void)
|
|
{
|
|
|
|
return (imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
|
|
}
|
|
|
|
uint32_t
|
|
imx_ccm_ahb_hz(void)
|
|
{
|
|
|
|
return (imx51_get_clock(IMX51CLK_AHB_CLK_ROOT));
|
|
}
|
|
|