af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
183 lines
9.0 KiB
C
183 lines
9.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Oleksandr Rybalko under sponsorship
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* from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* Registers definition for Freescale i.MX515 Synchronous Serial Interface */
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#define IMX51_SSI_STX0_REG 0x0000 /* SSI TX Data Register 0 */
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#define IMX51_SSI_STX1_REG 0x0004 /* SSI TX Data Register 1 */
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#define IMX51_SSI_SRX0_REG 0x0008 /* SSI RX Data Register 0 */
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#define IMX51_SSI_SRX1_REG 0x000C /* SSI RX Data Register 1 */
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#define IMX51_SSI_SCR_REG 0x0010 /* SSI Control Register */
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#define SSI_SCR_RFR_CLK_DIS (1 << 11) /* RX FC Disable */
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#define SSI_SCR_TFR_CLK_DIS (1 << 10) /* TX FC Disable */
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#define SSI_SCR_CLK_IST (1 << 9) /* Clock Idle */
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#define SSI_SCR_TCH_EN (1 << 8) /* 2Chan Enable */
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#define SSI_SCR_SYS_CLK_EN (1 << 7) /* System Clock En */
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#define SSI_SCR_MODE_NORMAL (0 << 5)
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#define SSI_SCR_MODE_I2S_MASTER (1 << 5)
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#define SSI_SCR_MODE_I2S_SLAVE (2 << 5)
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#define SSI_SCR_MODE_MASK (3 << 5)
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#define SSI_SCR_SYN (1 << 4) /* Sync Mode */
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#define SSI_SCR_NET (1 << 3) /* Network Mode */
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#define SSI_SCR_RE (1 << 2) /* RX Enable */
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#define SSI_SCR_TE (1 << 1) /* TX Enable */
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#define SSI_SCR_SSIEN (1 << 0) /* SSI Enable */
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#define IMX51_SSI_SISR_REG 0x0014 /* SSI Interrupt Status Register */
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#define SSI_SISR_RFRC (1 << 24) /* RX Frame Complete */
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#define SSI_SIR_TFRC (1 << 23) /* TX Frame Complete */
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#define SSI_SIR_CMDAU (1 << 18) /* Command Address Updated */
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#define SSI_SIR_CMDDU (1 << 17) /* Command Data Updated */
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#define SSI_SIR_RXT (1 << 16) /* RX Tag Updated */
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#define SSI_SIR_RDR1 (1 << 15) /* RX Data Ready 1 */
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#define SSI_SIR_RDR0 (1 << 14) /* RX Data Ready 0 */
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#define SSI_SIR_TDE1 (1 << 13) /* TX Data Reg Empty 1 */
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#define SSI_SIR_TDE0 (1 << 12) /* TX Data Reg Empty 0 */
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#define SSI_SIR_ROE1 (1 << 11) /* RXer Overrun Error 1 */
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#define SSI_SIR_ROE0 (1 << 10) /* RXer Overrun Error 0 */
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#define SSI_SIR_TUE1 (1 << 9) /* TXer Underrun Error 1 */
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#define SSI_SIR_TUE0 (1 << 8) /* TXer Underrun Error 0 */
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#define SSI_SIR_TFS (1 << 7) /* TX Frame Sync */
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#define SSI_SIR_RFS (1 << 6) /* RX Frame Sync */
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#define SSI_SIR_TLS (1 << 5) /* TX Last Time Slot */
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#define SSI_SIR_RLS (1 << 4) /* RX Last Time Slot */
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#define SSI_SIR_RFF1 (1 << 3) /* RX FIFO Full 1 */
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#define SSI_SIR_RFF0 (1 << 2) /* RX FIFO Full 0 */
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#define SSI_SIR_TFE1 (1 << 1) /* TX FIFO Empty 1 */
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#define SSI_SIR_TFE0 (1 << 0) /* TX FIFO Empty 0 */
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#define IMX51_SSI_SIER_REG 0x0018 /* SSI Interrupt Enable Register */
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/* 24-23 Enable Bit (See SISR) */
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#define SSI_SIER_RDMAE (1 << 22) /* RX DMA Enable */
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#define SSI_SIER_RIE (1 << 21) /* RX Interrupt Enable */
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#define SSI_SIER_TDMAE (1 << 20) /* TX DMA Enable */
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#define SSI_SIER_TIE (1 << 19) /* TX Interrupt Enable */
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/* 18-0 Enable Bits (See SISR) */
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#define IMX51_SSI_STCR_REG 0x001C /* SSI TX Configuration Register */
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#define SSI_STCR_TXBIT0 (1 << 9) /* TX Bit 0 */
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#define SSI_STCR_TFEN1 (1 << 8) /* TX FIFO Enable 1 */
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#define SSI_STCR_TFEN0 (1 << 7) /* TX FIFO Enable 0 */
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#define SSI_STCR_TFDIR (1 << 6) /* TX Frame Direction */
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#define SSI_STCR_TXDIR (1 << 5) /* TX Clock Direction */
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#define SSI_STCR_TSHFD (1 << 4) /* TX Shift Direction */
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#define SSI_STCR_TSCKP (1 << 3) /* TX Clock Polarity */
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#define SSI_STCR_TFSI (1 << 2) /* TX Frame Sync Invert */
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#define SSI_STCR_TFSL (1 << 1) /* TX Frame Sync Length */
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#define SSI_STCR_TEFS (1 << 0) /* TX Early Frame Sync */
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#define IMX51_SSI_SRCR_REG 0x0020 /* SSI RX Configuration Register */
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#define SSI_SRCR_RXEXT (1 << 10) /* RX Data Extension */
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#define SSI_SRCR_RXBIT0 (1 << 9) /* RX Bit 0 */
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#define SSI_SRCR_RFEN1 (1 << 8) /* RX FIFO Enable 1 */
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#define SSI_SRCR_RFEN0 (1 << 7) /* RX FIFO Enable 0 */
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#define SSI_SRCR_RFDIR (1 << 6) /* RX Frame Direction */
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#define SSI_SRCR_RXDIR (1 << 5) /* RX Clock Direction */
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#define SSI_SRCR_RSHFD (1 << 4) /* RX Shift Direction */
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#define SSI_SRCR_RSCKP (1 << 3) /* RX Clock Polarity */
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#define SSI_SRCR_RFSI (1 << 2) /* RX Frame Sync Invert */
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#define SSI_SRCR_RFSL (1 << 1) /* RX Frame Sync Length */
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#define SSI_SRCR_REFS (1 << 0) /* RX Early Frame Sync */
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#define IMX51_SSI_STCCR_REG 0x0024 /* TX Clock Control */
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#define IMX51_SSI_SRCCR_REG 0x0028 /* RX Clock Control */
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#define SSI_SXCCR_DIV2 (1 << 18) /* Divide By 2 */
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#define SSI_SXCCR_PSR (1 << 17) /* Prescaler Range */
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#define SSI_SXCCR_WL_MASK 0x0001e000
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#define SSI_SXCCR_WL_SHIFT 13 /* Word Length Control */
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#define SSI_SXCCR_DC_MASK 0x00001f00
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#define SSI_SXCCR_DC_SHIFT 8 /* Frame Rate Divider */
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#define SSI_SXCCR_PM_MASK 0x000000ff
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#define SSI_SXCCR_PM_SHIFT 0 /* Prescaler Modulus */
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#define IMX51_SSI_SFCSR_REG 0x002C /* SSI FIFO Control/Status Register */
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#define SSI_SFCSR_RFCNT1_MASK 0xf0000000
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#define SSI_SFCSR_RFCNT1_SHIFT 28 /* RX FIFO Counter 1 */
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#define SSI_SFCSR_TFCNT1_MASK 0x0f000000
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#define SSI_SFCSR_TFCNT1_SHIFT 24 /* TX FIFO Counter 1 */
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#define SSI_SFCSR_RFWM1_MASK 0x00f00000
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#define SSI_SFCSR_RFWM1_SHIFT 20 /* RX FIFO Full WaterMark 1 */
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#define SSI_SFCSR_TFWM1_MASK 0x000f0000
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#define SSI_SFCSR_TFWM1_SHIFT 16 /* TX FIFO Empty WaterMark 1 */
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#define SSI_SFCSR_RFCNT0_MASK 0x0000f000
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#define SSI_SFCSR_RFCNT0_SHIFT 12 /* RX FIFO Counter 0 */
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#define SSI_SFCSR_TFCNT0_MASK 0x00000f00
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#define SSI_SFCSR_TFCNT0_SHIFT 8 /* TX FIFO Counter 0 */
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#define SSI_SFCSR_RFWM0_MASK 0x000000f0
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#define SSI_SFCSR_RFWM0_SHIFT 4 /* RX FIFO Full WaterMark 0 */
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#define SSI_SFCSR_TFWM0_MASK 0x0000000f
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#define SSI_SFCSR_TFWM0_SHIFT 0 /* TX FIFO Empty WaterMark 0 */
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#define IMX51_SSI_STR_REG 0x0030 /* SSI Test Register1 */
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#define SSI_STR_TEST (1 << 15) /* Test Mode */
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#define SSI_STR_RCK2TCK (1 << 14) /* RX<->TX Clock Loop Back */
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#define SSI_STR_RFS2TFS (1 << 13) /* RX<->TX Frame Loop Back */
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#define SSI_STR_RXSTATE_MASK 0x00001f00
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#define SSI_STR_RXSTATE_SHIFT 8 /* RXer State Machine Status */
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#define SSI_STR_TXD2RXD (1 << 7) /* TX<->RX Data Loop Back */
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#define SSI_STR_TCK2RCK (1 << 6) /* TX<->RX Clock Loop Back */
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#define SSI_STR_TFS2RFS (1 << 5) /* TX<->RX Frame Loop Back */
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#define SSI_STR_TXSTATE_MASK 0x0000001f
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#define SSI_STR_TXSTATE_SHIFT 0 /* TXer State Machine Status */
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#define IMX51_SSI_SOR_REG 0x0034 /* SSI Option Register2 */
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#define SSI_SOR_CLKOFF (1 << 6) /* Clock Off */
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#define SSI_SOR_RX_CLR (1 << 5) /* RXer Clear */
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#define SSI_SOR_TX_CLR (1 << 4) /* TXer Clear */
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#define SSI_SOR_INIT (1 << 3) /* Initialize */
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#define SSI_SOR_WAIT_MASK 0x00000006
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#define SSI_SOR_INIT_SHIFT 1 /* Wait */
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#define SSI_SOR_SYNRST (1 << 0) /* Frame Sync Reset */
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#define IMX51_SSI_SACNT_REG 0x0038 /* SSI AC97 Control Register */
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#define SSI_SACNT_FRDIV_MASK 0x000007e0
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#define SSI_SACNT_FRDIV_SHIFT 5 /* Frame Rate Divider */
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#define SSI_SACNT_WR (1 << 4) /* Write Command */
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#define SSI_SACNT_RD (1 << 3) /* Read Command */
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#define SSI_SACNT_TIF (1 << 2) /* Tag in FIFO */
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#define SSI_SACNT_FV (1 << 1) /* Fixed/Variable Operation */
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#define SSI_SACNT_AC97EN (1 << 0) /* AC97 Mode Enable */
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#define IMX51_SSI_SACADD_REG 0x003C /* SSI AC97 Command Address Register */
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#define SSI_SACADD_MASK 0x0007ffff
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#define IMX51_SSI_SACDAT_REG 0x0040 /* SSI AC97 Command Data Register */
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#define SSI_SACDAT_MASK 0x000fffff
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#define IMX51_SSI_SATAG_REG 0x0044 /* SSI AC97 Tag Register */
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#define SSI_SATAG_MASK 0x0000ffff
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#define IMX51_SSI_STMSK_REG 0x0048 /* SSI TX Time Slot Mask Register */
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#define IMX51_SSI_SRMSK_REG 0x004C /* SSI RX Time Slot Mask Register */
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#define IMX51_SSI_SACCST_REG 0x0050 /* SSI AC97 Channel Status Register */
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#define IMX51_SSI_SACCEN_REG 0x0054 /* SSI AC97 Channel Enable Register */
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#define IMX51_SSI_SACCDIS_REG 0x0058 /* SSI AC97 Channel Disable Register */
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#define SSI_SAC_MASK 0x000003ff /* SACCST,SACCEN,SACCDIS */
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