244 lines
7.3 KiB
C
244 lines
7.3 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Vybrid Family 12-bit Analog to Digital Converter (ADC)
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* Chapter 37, Vybrid Reference Manual, Rev. 5, 07/2013
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/freescale/vybrid/vf_common.h>
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#include <arm/freescale/vybrid/vf_adc.h>
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#define ADC_HC0 0x00 /* Ctrl reg for hardware triggers */
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#define ADC_HC1 0x04 /* Ctrl reg for hardware triggers */
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#define HC_AIEN (1 << 7) /* Conversion Complete Int Control */
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#define HC_ADCH_M 0x1f /* Input Channel Select Mask */
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#define HC_ADCH_S 0 /* Input Channel Select Shift */
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#define ADC_HS 0x08 /* Status register for HW triggers */
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#define HS_COCO0 (1 << 0) /* Conversion Complete Flag */
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#define HS_COCO1 (1 << 1) /* Conversion Complete Flag */
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#define ADC_R0 0x0C /* Data result reg for HW triggers */
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#define ADC_R1 0x10 /* Data result reg for HW triggers */
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#define ADC_CFG 0x14 /* Configuration register */
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#define CFG_OVWREN (1 << 16) /* Data Overwrite Enable */
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#define CFG_AVGS_M 0x3 /* Hardware Average select Mask */
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#define CFG_AVGS_S 14 /* Hardware Average select Shift */
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#define CFG_ADTRG (1 << 13) /* Conversion Trigger Select */
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#define CFG_REFSEL_M 0x3 /* Voltage Reference Select Mask */
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#define CFG_REFSEL_S 11 /* Voltage Reference Select Shift */
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#define CFG_ADHSC (1 << 10) /* High Speed Configuration */
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#define CFG_ADSTS_M 0x3 /* Defines the sample time duration */
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#define CFG_ADSTS_S 8 /* Defines the sample time duration */
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#define CFG_ADLPC (1 << 7) /* Low-Power Configuration */
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#define CFG_ADIV_M 0x3 /* Clock Divide Select */
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#define CFG_ADIV_S 5 /* Clock Divide Select */
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#define CFG_ADLSMP (1 << 4) /* Long Sample Time Configuration */
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#define CFG_MODE_M 0x3 /* Conversion Mode Selection Mask */
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#define CFG_MODE_S 2 /* Conversion Mode Selection Shift */
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#define CFG_MODE_12 0x2 /* 12-bit mode */
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#define CFG_ADICLK_M 0x3 /* Input Clock Select Mask */
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#define CFG_ADICLK_S 0 /* Input Clock Select Shift */
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#define ADC_GC 0x18 /* General control register */
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#define GC_CAL (1 << 7) /* Calibration */
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#define GC_ADCO (1 << 6) /* Continuous Conversion Enable */
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#define GC_AVGE (1 << 5) /* Hardware average enable */
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#define GC_ACFE (1 << 4) /* Compare Function Enable */
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#define GC_ACFGT (1 << 3) /* Compare Function Greater Than En */
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#define GC_ACREN (1 << 2) /* Compare Function Range En */
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#define GC_DMAEN (1 << 1) /* DMA Enable */
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#define GC_ADACKEN (1 << 0) /* Asynchronous clock output enable */
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#define ADC_GS 0x1C /* General status register */
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#define GS_AWKST (1 << 2) /* Asynchronous wakeup int status */
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#define GS_CALF (1 << 1) /* Calibration Failed Flag */
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#define GS_ADACT (1 << 0) /* Conversion Active */
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#define ADC_CV 0x20 /* Compare value register */
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#define CV_CV2_M 0xfff /* Compare Value 2 Mask */
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#define CV_CV2_S 16 /* Compare Value 2 Shift */
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#define CV_CV1_M 0xfff /* Compare Value 1 Mask */
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#define CV_CV1_S 0 /* Compare Value 1 Shift */
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#define ADC_OFS 0x24 /* Offset correction value register */
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#define OFS_SIGN 12 /* Sign bit */
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#define OFS_M 0xfff /* Offset value Mask */
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#define OFS_S 0 /* Offset value Shift */
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#define ADC_CAL 0x28 /* Calibration value register */
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#define CAL_CODE_M 0xf /* Calibration Result Value Mask */
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#define CAL_CODE_S 0 /* Calibration Result Value Shift */
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#define ADC_PCTL 0x30 /* Pin control register */
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struct adc_softc {
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struct resource *res[2];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih;
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};
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struct adc_softc *adc_sc;
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static struct resource_spec adc_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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adc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,mvf600-adc"))
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return (ENXIO);
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device_set_desc(dev, "Vybrid Family "
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"12-bit Analog to Digital Converter");
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return (BUS_PROBE_DEFAULT);
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}
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static void
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adc_intr(void *arg)
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{
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struct adc_softc *sc;
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sc = arg;
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/* Conversation complete */
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}
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uint32_t
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adc_read(void)
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{
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struct adc_softc *sc;
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sc = adc_sc;
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if (sc == NULL)
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return (0);
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return (READ4(sc, ADC_R0));
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}
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uint32_t
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adc_enable(int channel)
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{
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struct adc_softc *sc;
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int reg;
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sc = adc_sc;
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if (sc == NULL)
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return (1);
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reg = READ4(sc, ADC_HC0);
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reg &= ~(HC_ADCH_M << HC_ADCH_S);
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reg |= (channel << HC_ADCH_S);
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WRITE4(sc, ADC_HC0, reg);
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return (0);
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}
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static int
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adc_attach(device_t dev)
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{
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struct adc_softc *sc;
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int err;
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int reg;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, adc_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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adc_sc = sc;
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/* Setup interrupt handler */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, adc_intr, sc, &sc->ih);
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if (err) {
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device_printf(dev, "Unable to alloc interrupt resource.\n");
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return (ENXIO);
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}
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/* Configure 12-bit mode */
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reg = READ4(sc, ADC_CFG);
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reg &= ~(CFG_MODE_M << CFG_MODE_S);
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reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */
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WRITE4(sc, ADC_CFG, reg);
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/* Configure for continuous conversion */
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reg = READ4(sc, ADC_GC);
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reg |= (GC_ADCO | GC_AVGE);
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WRITE4(sc, ADC_GC, reg);
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/* Disable interrupts */
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reg = READ4(sc, ADC_HC0);
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reg &= HC_AIEN;
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WRITE4(sc, ADC_HC0, reg);
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return (0);
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}
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static device_method_t adc_methods[] = {
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DEVMETHOD(device_probe, adc_probe),
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DEVMETHOD(device_attach, adc_attach),
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{ 0, 0 }
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};
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static driver_t adc_driver = {
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"adc",
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adc_methods,
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sizeof(struct adc_softc),
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};
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static devclass_t adc_devclass;
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DRIVER_MODULE(adc, simplebus, adc_driver, adc_devclass, 0, 0);
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