af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
189 lines
7.4 KiB
C
189 lines
7.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define DMA_CR 0x000 /* Control */
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#define DMA_ES 0x004 /* Error Status */
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#define DMA_ERQ 0x00C /* Enable Request */
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#define DMA_EEI 0x014 /* Enable Error Interrupt */
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#define DMA_CEEI 0x018 /* Clear Enable Error Interrupt */
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#define DMA_SEEI 0x019 /* Set Enable Error Interrupt */
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#define DMA_CERQ 0x01A /* Clear Enable Request */
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#define DMA_SERQ 0x01B /* Set Enable Request */
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#define DMA_CDNE 0x01C /* Clear DONE Status Bit */
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#define DMA_SSRT 0x01D /* Set START Bit */
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#define DMA_CERR 0x01E /* Clear Error */
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#define CERR_CAEI (1 << 6) /* Clear All Error Indicators */
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#define DMA_CINT 0x01F /* Clear Interrupt Request */
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#define CINT_CAIR (1 << 6) /* Clear All Interrupt Requests */
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#define DMA_INT 0x024 /* Interrupt Request */
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#define DMA_ERR 0x02C /* Error */
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#define DMA_HRS 0x034 /* Hardware Request Status */
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#define DMA_EARS 0x044 /* Enable Asynchronous Request in Stop */
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#define DMA_DCHPRI3 0x100 /* Channel n Priority */
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#define DMA_DCHPRI2 0x101 /* Channel n Priority */
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#define DMA_DCHPRI1 0x102 /* Channel n Priority */
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#define DMA_DCHPRI0 0x103 /* Channel n Priority */
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#define DMA_DCHPRI7 0x104 /* Channel n Priority */
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#define DMA_DCHPRI6 0x105 /* Channel n Priority */
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#define DMA_DCHPRI5 0x106 /* Channel n Priority */
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#define DMA_DCHPRI4 0x107 /* Channel n Priority */
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#define DMA_DCHPRI11 0x108 /* Channel n Priority */
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#define DMA_DCHPRI10 0x109 /* Channel n Priority */
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#define DMA_DCHPRI9 0x10A /* Channel n Priority */
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#define DMA_DCHPRI8 0x10B /* Channel n Priority */
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#define DMA_DCHPRI15 0x10C /* Channel n Priority */
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#define DMA_DCHPRI14 0x10D /* Channel n Priority */
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#define DMA_DCHPRI13 0x10E /* Channel n Priority */
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#define DMA_DCHPRI12 0x10F /* Channel n Priority */
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#define DMA_DCHPRI19 0x110 /* Channel n Priority */
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#define DMA_DCHPRI18 0x111 /* Channel n Priority */
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#define DMA_DCHPRI17 0x112 /* Channel n Priority */
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#define DMA_DCHPRI16 0x113 /* Channel n Priority */
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#define DMA_DCHPRI23 0x114 /* Channel n Priority */
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#define DMA_DCHPRI22 0x115 /* Channel n Priority */
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#define DMA_DCHPRI21 0x116 /* Channel n Priority */
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#define DMA_DCHPRI20 0x117 /* Channel n Priority */
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#define DMA_DCHPRI27 0x118 /* Channel n Priority */
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#define DMA_DCHPRI26 0x119 /* Channel n Priority */
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#define DMA_DCHPRI25 0x11A /* Channel n Priority */
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#define DMA_DCHPRI24 0x11B /* Channel n Priority */
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#define DMA_DCHPRI31 0x11C /* Channel n Priority */
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#define DMA_DCHPRI30 0x11D /* Channel n Priority */
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#define DMA_DCHPRI29 0x11E /* Channel n Priority */
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#define DMA_DCHPRI28 0x11F /* Channel n Priority */
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#define DMA_TCDn_SADDR(n) (0x00 + 0x20 * n) /* Source Address */
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#define DMA_TCDn_SOFF(n) (0x04 + 0x20 * n) /* Signed Source Address Offset */
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#define DMA_TCDn_ATTR(n) (0x06 + 0x20 * n) /* Transfer Attributes */
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#define DMA_TCDn_NBYTES_MLNO(n) (0x08 + 0x20 * n) /* Minor Byte Count */
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#define DMA_TCDn_NBYTES_MLOFFNO(n) (0x08 + 0x20 * n) /* Signed Minor Loop Offset */
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#define DMA_TCDn_NBYTES_MLOFFYES(n) (0x08 + 0x20 * n) /* Signed Minor Loop Offset */
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#define DMA_TCDn_SLAST(n) (0x0C + 0x20 * n) /* Last Source Address Adjustment */
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#define DMA_TCDn_DADDR(n) (0x10 + 0x20 * n) /* Destination Address */
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#define DMA_TCDn_DOFF(n) (0x14 + 0x20 * n) /* Signed Destination Address Offset */
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#define DMA_TCDn_CITER_ELINKYES(n) (0x16 + 0x20 * n) /* Current Minor Loop Link, Major Loop Count */
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#define DMA_TCDn_CITER_ELINKNO(n) (0x16 + 0x20 * n)
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#define DMA_TCDn_DLASTSGA(n) (0x18 + 0x20 * n) /* Last Dst Addr Adjustment/Scatter Gather Address */
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#define DMA_TCDn_CSR(n) (0x1C + 0x20 * n) /* Control and Status */
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#define DMA_TCDn_BITER_ELINKYES(n) (0x1E + 0x20 * n) /* Beginning Minor Loop Link, Major Loop Count */
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#define DMA_TCDn_BITER_ELINKNO(n) (0x1E + 0x20 * n) /* Beginning Minor Loop Link, Major Loop Count */
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#define TCD_CSR_START (1 << 0)
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#define TCD_CSR_INTMAJOR (1 << 1)
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#define TCD_CSR_INTHALF (1 << 2)
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#define TCD_CSR_DREQ (1 << 3)
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#define TCD_CSR_ESG (1 << 4)
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#define TCD_CSR_MAJORELINK (1 << 5)
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#define TCD_CSR_ACTIVE (1 << 6)
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#define TCD_CSR_DONE (1 << 7)
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#define TCD_CSR_MAJORELINKCH_SHIFT 8
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#define TCD_ATTR_SMOD_SHIFT 11 /* Source Address Modulo */
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#define TCD_ATTR_SSIZE_SHIFT 8 /* Source Data Transfer Size */
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#define TCD_ATTR_DMOD_SHIFT 3 /* Dst Address Modulo */
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#define TCD_ATTR_DSIZE_SHIFT 0 /* Dst Data Transfer Size */
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#define TCD_READ4(_sc, _reg) \
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bus_space_read_4(_sc->bst_tcd, _sc->bsh_tcd, _reg)
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#define TCD_WRITE4(_sc, _reg, _val) \
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bus_space_write_4(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
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#define TCD_READ2(_sc, _reg) \
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bus_space_read_2(_sc->bst_tcd, _sc->bsh_tcd, _reg)
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#define TCD_WRITE2(_sc, _reg, _val) \
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bus_space_write_2(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
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#define TCD_READ1(_sc, _reg) \
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bus_space_read_1(_sc->bst_tcd, _sc->bsh_tcd, _reg)
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#define TCD_WRITE1(_sc, _reg, _val) \
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bus_space_write_1(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
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#define EDMA_NUM_DEVICES 2
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#define EDMA_NUM_CHANNELS 32
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#define NCHAN_PER_MUX 16
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struct tcd_conf {
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bus_addr_t saddr;
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bus_addr_t daddr;
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uint32_t nbytes;
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uint32_t nmajor;
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uint32_t majorelink;
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uint32_t majorelinkch;
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uint32_t esg;
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uint32_t smod;
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uint32_t dmod;
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uint32_t soff;
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uint32_t doff;
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uint32_t ssize;
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uint32_t dsize;
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uint32_t slast;
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uint32_t dlast_sga;
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uint32_t channel;
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uint32_t (*ih)(void *, int);
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void *ih_user;
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};
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/*
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* TCD struct is described at
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* Vybrid Reference Manual, Rev. 5, 07/2013
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*
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* Should be used for Scatter/Gathering feature.
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*/
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struct TCD {
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uint32_t saddr;
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uint16_t attr;
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uint16_t soff;
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uint32_t nbytes;
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uint32_t slast;
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uint32_t daddr;
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uint16_t citer;
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uint16_t doff;
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uint32_t dlast_sga;
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uint16_t biter;
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uint16_t csr;
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} __packed;
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struct edma_softc {
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device_t dev;
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struct resource *res[4];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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bus_space_tag_t bst_tcd;
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bus_space_handle_t bsh_tcd;
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void *tc_ih;
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void *err_ih;
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uint32_t device_id;
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int (*channel_configure) (struct edma_softc *, int, int);
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int (*channel_free) (struct edma_softc *, int);
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int (*dma_request) (struct edma_softc *, int);
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int (*dma_setup) (struct edma_softc *, struct tcd_conf *);
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int (*dma_stop) (struct edma_softc *, int);
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};
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