d5d4dd38b4
The AXI bridge is different between ARMADA 38x and 8K, and both platforms needs specific setup to mitigate HW issues with accessing RTC registers. MFC after: 2 weeks
371 lines
9.5 KiB
C
371 lines
9.5 KiB
C
/*-
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* Copyright (c) 2015 Semihalf.
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* Copyright (c) 2015 Stormshield.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/time.h>
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#include <sys/proc.h>
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#include <sys/conf.h>
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#include <sys/rman.h>
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#include <sys/clock.h>
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#include <sys/systm.h>
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#include <sys/mutex.h>
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#include <sys/types.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "clock_if.h"
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#define RTC_RES_US 1000000
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#define HALF_OF_SEC_NS 500000000
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#define RTC_STATUS 0x0
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#define RTC_TIME 0xC
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#define RTC_TEST_CONFIG 0x1C
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#define RTC_IRQ_1_CONFIG 0x4
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#define RTC_IRQ_2_CONFIG 0x8
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#define RTC_ALARM_1 0x10
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#define RTC_ALARM_2 0x14
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#define RTC_CLOCK_CORR 0x18
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#define RTC_NOMINAL_TIMING 0x2000
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#define RTC_NOMINAL_TIMING_MASK 0x7fff
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#define RTC_STATUS_ALARM1_MASK 0x1
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#define RTC_STATUS_ALARM2_MASK 0x2
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#define MV_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mutex)
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#define MV_RTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->mutex)
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#define A38X_RTC_BRIDGE_TIMING_CTRL 0x0
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#define A38X_RTC_WRCLK_PERIOD_SHIFT 0
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#define A38X_RTC_WRCLK_PERIOD_MASK 0x00000003FF
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#define A38X_RTC_WRCLK_PERIOD_MAX 0x3FF
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#define A38X_RTC_READ_OUTPUT_DELAY_SHIFT 26
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#define A38X_RTC_READ_OUTPUT_DELAY_MASK 0x007C000000
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#define A38X_RTC_READ_OUTPUT_DELAY_MAX 0x1F
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#define A8K_RTC_BRIDGE_TIMING_CTRL0 0x0
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#define A8K_RTC_WRCLK_PERIOD_SHIFT 0
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#define A8K_RTC_WRCLK_PERIOD_MASK 0x000000FFFF
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#define A8K_RTC_WRCLK_PERIOD_VAL 0x3FF
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#define A8K_RTC_WRCLK_SETUP_SHIFT 16
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#define A8K_RTC_WRCLK_SETUP_MASK 0x00FFFF0000
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#define A8K_RTC_WRCLK_SETUP_VAL 29
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#define A8K_RTC_BRIDGE_TIMING_CTRL1 0x4
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#define A8K_RTC_READ_OUTPUT_DELAY_SHIFT 0
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#define A8K_RTC_READ_OUTPUT_DELAY_MASK 0x000000FFFF
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#define A8K_RTC_READ_OUTPUT_DELAY_VAL 0x3F
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#define RTC_RES 0
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#define RTC_SOC_RES 1
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static struct resource_spec res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ -1, 0 }
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};
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struct mv_rtc_softc {
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device_t dev;
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struct resource *res[2];
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struct mtx mutex;
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int rtc_type;
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};
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static int mv_rtc_probe(device_t dev);
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static int mv_rtc_attach(device_t dev);
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static int mv_rtc_detach(device_t dev);
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static int mv_rtc_gettime(device_t dev, struct timespec *ts);
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static int mv_rtc_settime(device_t dev, struct timespec *ts);
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static inline uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc,
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bus_size_t off);
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static inline int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off,
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uint32_t val);
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static inline void mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc);
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static inline void mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc);
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static device_method_t mv_rtc_methods[] = {
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DEVMETHOD(device_probe, mv_rtc_probe),
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DEVMETHOD(device_attach, mv_rtc_attach),
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DEVMETHOD(device_detach, mv_rtc_detach),
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DEVMETHOD(clock_gettime, mv_rtc_gettime),
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DEVMETHOD(clock_settime, mv_rtc_settime),
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{ 0, 0 },
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};
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static driver_t mv_rtc_driver = {
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"rtc",
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mv_rtc_methods,
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sizeof(struct mv_rtc_softc),
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};
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#define RTC_A38X 1
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#define RTC_A8K 2
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static struct ofw_compat_data mv_rtc_compat[] = {
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{"marvell,armada-380-rtc", RTC_A38X},
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{"marvell,armada-8k-rtc", RTC_A8K},
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{NULL, 0},
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};
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static devclass_t mv_rtc_devclass;
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DRIVER_MODULE(a38x_rtc, simplebus, mv_rtc_driver, mv_rtc_devclass, 0, 0);
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static void
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mv_rtc_reset(device_t dev)
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{
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struct mv_rtc_softc *sc;
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sc = device_get_softc(dev);
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/* Reset Test register */
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mv_rtc_reg_write(sc, RTC_TEST_CONFIG, 0);
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DELAY(500000);
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/* Reset Time register */
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mv_rtc_reg_write(sc, RTC_TIME, 0);
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DELAY(62);
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/* Reset Status register */
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mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK));
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DELAY(62);
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/* Turn off Int1 and Int2 sources & clear the Alarm count */
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mv_rtc_reg_write(sc, RTC_IRQ_1_CONFIG, 0);
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mv_rtc_reg_write(sc, RTC_IRQ_2_CONFIG, 0);
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mv_rtc_reg_write(sc, RTC_ALARM_1, 0);
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mv_rtc_reg_write(sc, RTC_ALARM_2, 0);
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/* Setup nominal register access timing */
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mv_rtc_reg_write(sc, RTC_CLOCK_CORR, RTC_NOMINAL_TIMING);
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/* Reset Time register */
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mv_rtc_reg_write(sc, RTC_TIME, 0);
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DELAY(10);
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/* Reset Status register */
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mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK));
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DELAY(50);
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}
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static int
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mv_rtc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Marvell Integrated RTC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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mv_rtc_attach(device_t dev)
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{
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struct mv_rtc_softc *sc;
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int unit, ret;
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unit = device_get_unit(dev);
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->rtc_type = ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data;
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mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN);
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ret = bus_alloc_resources(dev, res_spec, sc->res);
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if (ret != 0) {
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device_printf(dev, "could not allocate resources\n");
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mtx_destroy(&sc->mutex);
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return (ENXIO);
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}
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switch (sc->rtc_type) {
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case RTC_A38X:
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mv_rtc_configure_bus_a38x(sc);
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break;
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case RTC_A8K:
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mv_rtc_configure_bus_a8k(sc);
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break;
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default:
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panic("Unknown RTC type: %d", sc->rtc_type);
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}
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clock_register(dev, RTC_RES_US);
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return (0);
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}
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static int
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mv_rtc_detach(device_t dev)
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{
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struct mv_rtc_softc *sc;
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sc = device_get_softc(dev);
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mtx_destroy(&sc->mutex);
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bus_release_resources(dev, res_spec, sc->res);
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return (0);
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}
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static int
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mv_rtc_gettime(device_t dev, struct timespec *ts)
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{
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struct mv_rtc_softc *sc;
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uint32_t val, val_check;
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sc = device_get_softc(dev);
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MV_RTC_LOCK(sc);
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/*
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* According to HW Errata, if more than one second is detected
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* between two time reads, then at least one of the reads gave
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* an invalid value.
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*/
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do {
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val = mv_rtc_reg_read(sc, RTC_TIME);
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DELAY(100);
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val_check = mv_rtc_reg_read(sc, RTC_TIME);
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} while ((val_check - val) > 1);
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MV_RTC_UNLOCK(sc);
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ts->tv_sec = val_check;
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/* RTC resolution is 1 sec */
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ts->tv_nsec = 0;
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return (0);
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}
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static int
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mv_rtc_settime(device_t dev, struct timespec *ts)
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{
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struct mv_rtc_softc *sc;
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sc = device_get_softc(dev);
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/* RTC resolution is 1 sec */
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if (ts->tv_nsec >= HALF_OF_SEC_NS)
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ts->tv_sec++;
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ts->tv_nsec = 0;
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MV_RTC_LOCK(sc);
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if ((mv_rtc_reg_read(sc, RTC_CLOCK_CORR) & RTC_NOMINAL_TIMING_MASK) !=
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RTC_NOMINAL_TIMING) {
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/* RTC was not resetted yet */
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mv_rtc_reset(dev);
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}
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/*
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* According to errata FE-3124064, Write to RTC TIME register
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* may fail. As a workaround, before writing to RTC TIME register,
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* issue a dummy write of 0x0 twice to RTC Status register.
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*/
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mv_rtc_reg_write(sc, RTC_STATUS, 0x0);
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mv_rtc_reg_write(sc, RTC_STATUS, 0x0);
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mv_rtc_reg_write(sc, RTC_TIME, ts->tv_sec);
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MV_RTC_UNLOCK(sc);
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return (0);
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}
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static inline uint32_t
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mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->res[RTC_RES], off));
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}
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/*
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* According to the datasheet, the OS should wait 5us after every
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* register write to the RTC hard macro so that the required update
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* can occur without holding off the system bus
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*/
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static inline int
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mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->res[RTC_RES], off, val);
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DELAY(5);
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return (0);
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}
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static inline void
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mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc)
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{
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int val;
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val = bus_read_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL);
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val &= ~(A38X_RTC_WRCLK_PERIOD_MASK | A38X_RTC_READ_OUTPUT_DELAY_MASK);
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val |= A38X_RTC_WRCLK_PERIOD_MAX << A38X_RTC_WRCLK_PERIOD_SHIFT;
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val |= A38X_RTC_READ_OUTPUT_DELAY_MAX << A38X_RTC_READ_OUTPUT_DELAY_SHIFT;
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bus_write_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL, val);
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}
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static inline void
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mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc)
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{
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int val;
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val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0);
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val &= ~(A8K_RTC_WRCLK_PERIOD_MASK | A8K_RTC_WRCLK_SETUP_MASK);
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val |= A8K_RTC_WRCLK_PERIOD_VAL << A8K_RTC_WRCLK_PERIOD_SHIFT;
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val |= A8K_RTC_WRCLK_SETUP_VAL << A8K_RTC_WRCLK_SETUP_SHIFT;
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bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val);
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val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0);
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val &= ~A8K_RTC_READ_OUTPUT_DELAY_MASK;
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val |= A8K_RTC_READ_OUTPUT_DELAY_VAL << A8K_RTC_READ_OUTPUT_DELAY_SHIFT;
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bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val);
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}
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