581 lines
12 KiB
C
581 lines
12 KiB
C
/* $NetBSD: db_interface.c,v 1.2 1997/09/16 19:07:19 thorpej Exp $ */
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/* $FreeBSD$ */
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/*
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* Mach Operating System
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* Copyright (c) 1992,1991,1990 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*
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* db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
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*/
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/*
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* Parts of this file are derived from Mach 3:
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*
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* File: alpha_instruction.c
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 6/92
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*/
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/*
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* Interface to DDB.
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*
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* Modified for NetBSD/alpha by:
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*
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* Christopher G. Demetriou, Carnegie Mellon University
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*
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* Jason R. Thorpe, Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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/* __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.2 1997/09/16 19:07:19 thorpej Exp $"); */
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/cons.h>
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#include <sys/ktr.h>
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#include <sys/lock.h>
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#include <sys/pcpu.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <machine/db_machdep.h>
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#include <machine/pal.h>
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#include <machine/prom.h>
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#include <alpha/alpha/db_instruction.h>
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#include <ddb/ddb.h>
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#include <ddb/db_access.h>
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#include <ddb/db_sym.h>
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#include <ddb/db_variables.h>
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#include <machine/setjmp.h>
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static jmp_buf *db_nofault = 0;
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extern jmp_buf db_jmpbuf;
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extern void gdb_handle_exception(db_regs_t *, int, int);
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#if 0
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extern char *trap_type[];
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extern int trap_types;
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#endif
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int db_active;
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void ddbprinttrap(unsigned long, unsigned long, unsigned long,
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unsigned long);
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struct db_variable db_regs[] = {
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{ "v0", &ddb_regs.tf_regs[FRAME_V0], FCN_NULL },
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{ "t0", &ddb_regs.tf_regs[FRAME_T0], FCN_NULL },
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{ "t1", &ddb_regs.tf_regs[FRAME_T1], FCN_NULL },
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{ "t2", &ddb_regs.tf_regs[FRAME_T2], FCN_NULL },
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{ "t3", &ddb_regs.tf_regs[FRAME_T3], FCN_NULL },
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{ "t4", &ddb_regs.tf_regs[FRAME_T4], FCN_NULL },
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{ "t5", &ddb_regs.tf_regs[FRAME_T5], FCN_NULL },
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{ "t6", &ddb_regs.tf_regs[FRAME_T6], FCN_NULL },
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{ "t7", &ddb_regs.tf_regs[FRAME_T7], FCN_NULL },
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{ "s0", &ddb_regs.tf_regs[FRAME_S0], FCN_NULL },
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{ "s1", &ddb_regs.tf_regs[FRAME_S1], FCN_NULL },
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{ "s2", &ddb_regs.tf_regs[FRAME_S2], FCN_NULL },
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{ "s3", &ddb_regs.tf_regs[FRAME_S3], FCN_NULL },
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{ "s4", &ddb_regs.tf_regs[FRAME_S4], FCN_NULL },
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{ "s5", &ddb_regs.tf_regs[FRAME_S5], FCN_NULL },
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{ "s6", &ddb_regs.tf_regs[FRAME_S6], FCN_NULL },
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{ "a0", &ddb_regs.tf_regs[FRAME_A0], FCN_NULL },
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{ "a1", &ddb_regs.tf_regs[FRAME_A1], FCN_NULL },
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{ "a2", &ddb_regs.tf_regs[FRAME_A2], FCN_NULL },
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{ "a3", &ddb_regs.tf_regs[FRAME_A3], FCN_NULL },
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{ "a4", &ddb_regs.tf_regs[FRAME_A4], FCN_NULL },
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{ "a5", &ddb_regs.tf_regs[FRAME_A5], FCN_NULL },
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{ "t8", &ddb_regs.tf_regs[FRAME_T8], FCN_NULL },
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{ "t9", &ddb_regs.tf_regs[FRAME_T9], FCN_NULL },
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{ "t10", &ddb_regs.tf_regs[FRAME_T10], FCN_NULL },
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{ "t11", &ddb_regs.tf_regs[FRAME_T11], FCN_NULL },
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{ "ra", &ddb_regs.tf_regs[FRAME_RA], FCN_NULL },
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{ "t12", &ddb_regs.tf_regs[FRAME_T12], FCN_NULL },
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{ "at", &ddb_regs.tf_regs[FRAME_AT], FCN_NULL },
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{ "gp", &ddb_regs.tf_regs[FRAME_GP], FCN_NULL },
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{ "sp", &ddb_regs.tf_regs[FRAME_SP], FCN_NULL },
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{ "pc", &ddb_regs.tf_regs[FRAME_PC], FCN_NULL },
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{ "ps", &ddb_regs.tf_regs[FRAME_PS], FCN_NULL },
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{ "ai", &ddb_regs.tf_regs[FRAME_T11], FCN_NULL },
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{ "pv", &ddb_regs.tf_regs[FRAME_T12], FCN_NULL },
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};
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struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
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/*
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* Print trap reason.
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*/
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void
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ddbprinttrap(a0, a1, a2, entry)
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unsigned long a0, a1, a2, entry;
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{
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/* XXX Implement. */
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printf("ddbprinttrap(0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", a0, a1, a2,
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entry);
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}
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/*
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* ddb_trap - field a kernel trap
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*/
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int
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kdb_trap(a0, a1, a2, entry, regs)
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unsigned long a0, a1, a2, entry;
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db_regs_t *regs;
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{
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int ddb_mode = !(boothowto & RB_GDB);
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register_t s;
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/*
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* Don't bother checking for usermode, since a benign entry
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* by the kernel (call to Debugger() or a breakpoint) has
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* already checked for usermode. If neither of those
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* conditions exist, something Bad has happened.
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*/
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if (entry != ALPHA_KENTRY_IF ||
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(a0 != ALPHA_IF_CODE_BUGCHK && a0 != ALPHA_IF_CODE_BPT
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&& a0 != ALPHA_IF_CODE_GENTRAP)) {
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#if 0
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if (ddb_mode) {
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db_printf("ddbprinttrap from 0x%lx\n", /* XXX */
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regs->tf_regs[FRAME_PC]);
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ddbprinttrap(a0, a1, a2, entry);
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/*
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* Tell caller "We did NOT handle the trap."
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* Caller should panic, or whatever.
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*/
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return (0);
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}
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#endif
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if (db_nofault) {
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jmp_buf *no_fault = db_nofault;
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db_nofault = 0;
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longjmp(*no_fault, 1);
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}
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}
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/*
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* XXX Should switch to DDB's own stack, here.
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*/
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ddb_regs = *regs;
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s = intr_disable();
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#ifdef SMP
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#ifdef DIAGNOSTIC
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db_printf("stopping %x\n", PCPU_GET(other_cpus));
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#endif
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stop_cpus(PCPU_GET(other_cpus));
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#ifdef DIAGNOSTIC
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db_printf("stopped_cpus=%x\n", stopped_cpus);
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#endif
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#endif
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db_active++;
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if (ddb_mode) {
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cndbctl(TRUE); /* DDB active, unblank video */
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db_trap(entry, a0); /* Where the work happens */
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cndbctl(FALSE); /* DDB inactive */
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} else
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gdb_handle_exception(&ddb_regs, entry, a0);
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db_active--;
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#ifdef SMP
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restart_cpus(stopped_cpus);
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#endif
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intr_restore(s);
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*regs = ddb_regs;
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/*
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* Tell caller "We HAVE handled the trap."
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*/
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return (1);
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}
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/*
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* Read bytes from kernel address space for debugger.
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*/
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void
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db_read_bytes(addr, size, data)
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vm_offset_t addr;
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register size_t size;
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register char *data;
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{
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register char *src;
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db_nofault = &db_jmpbuf;
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src = (char *)addr;
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while (size-- > 0)
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*data++ = *src++;
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db_nofault = 0;
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}
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/*
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* Write bytes to kernel address space for debugger.
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*/
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void
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db_write_bytes(addr, size, data)
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vm_offset_t addr;
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register size_t size;
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register char *data;
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{
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register char *dst;
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db_nofault = &db_jmpbuf;
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dst = (char *)addr;
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while (size-- > 0)
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*dst++ = *data++;
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alpha_pal_imb();
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db_nofault = 0;
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}
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void
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Debugger(const char* msg)
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{
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u_int saveintr;
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printf("%s\n", msg);
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saveintr = alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH);
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__asm("call_pal 0x81"); /* XXX bugchk */
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alpha_pal_swpipl(saveintr);
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}
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/*
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* Alpha-specific ddb commands:
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*
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* halt set halt bit in rpb and halt
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* reboot set reboot bit in rpb and halt
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*/
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DB_COMMAND(halt, db_mach_halt)
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{
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prom_halt(1);
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}
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DB_COMMAND(reboot, db_mach_reboot)
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{
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prom_halt(0);
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}
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/*
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* Map Alpha register numbers to trapframe/db_regs_t offsets.
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*/
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static int reg_to_frame[32] = {
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FRAME_V0,
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FRAME_T0,
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FRAME_T1,
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FRAME_T2,
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FRAME_T3,
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FRAME_T4,
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FRAME_T5,
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FRAME_T6,
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FRAME_T7,
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FRAME_S0,
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FRAME_S1,
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FRAME_S2,
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FRAME_S3,
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FRAME_S4,
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FRAME_S5,
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FRAME_S6,
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FRAME_A0,
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FRAME_A1,
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FRAME_A2,
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FRAME_A3,
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FRAME_A4,
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FRAME_A5,
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FRAME_T8,
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FRAME_T9,
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FRAME_T10,
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FRAME_T11,
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FRAME_RA,
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FRAME_T12,
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FRAME_AT,
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FRAME_GP,
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FRAME_SP,
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-1, /* zero */
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};
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u_long
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db_register_value(regs, regno)
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db_regs_t *regs;
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int regno;
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{
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if (regno > 31 || regno < 0) {
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db_printf(" **** STRANGE REGISTER NUMBER %d **** ", regno);
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return (0);
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}
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if (regno == 31)
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return (0);
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return (regs->tf_regs[reg_to_frame[regno]]);
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}
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/*
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* Support functions for software single-step.
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*/
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boolean_t
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db_inst_call(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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return ((insn.branch_format.opcode == op_bsr) ||
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((insn.jump_format.opcode == op_j) &&
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(insn.jump_format.action & 1)));
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}
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boolean_t
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db_inst_return(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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return ((insn.jump_format.opcode == op_j) &&
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(insn.jump_format.action == op_ret));
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}
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boolean_t
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db_inst_trap_return(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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return ((insn.pal_format.opcode == op_pal) &&
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(insn.pal_format.function == PAL_OSF1_rti));
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}
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boolean_t
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db_inst_branch(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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switch (insn.branch_format.opcode) {
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case op_j:
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case op_br:
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case op_fbeq:
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case op_fblt:
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case op_fble:
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case op_fbne:
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case op_fbge:
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case op_fbgt:
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case op_blbc:
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case op_beq:
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case op_blt:
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case op_ble:
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case op_blbs:
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case op_bne:
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case op_bge:
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case op_bgt:
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return (TRUE);
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}
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return (FALSE);
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}
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boolean_t
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db_inst_unconditional_flow_transfer(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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switch (insn.branch_format.opcode) {
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case op_j:
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case op_br:
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return (TRUE);
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case op_pal:
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switch (insn.pal_format.function) {
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case PAL_OSF1_retsys:
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case PAL_OSF1_rti:
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case PAL_OSF1_callsys:
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return (TRUE);
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}
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}
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return (FALSE);
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}
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#if 0
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boolean_t
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db_inst_spill(ins, regn)
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int ins, regn;
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{
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alpha_instruction insn;
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insn.bits = ins;
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return ((insn.mem_format.opcode == op_stq) &&
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(insn.mem_format.rd == regn));
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}
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#endif
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boolean_t
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db_inst_load(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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/* Loads. */
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if (insn.mem_format.opcode == op_ldbu ||
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insn.mem_format.opcode == op_ldq_u ||
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insn.mem_format.opcode == op_ldwu)
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return (TRUE);
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if ((insn.mem_format.opcode >= op_ldf) &&
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(insn.mem_format.opcode <= op_ldt))
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return (TRUE);
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if ((insn.mem_format.opcode >= op_ldl) &&
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(insn.mem_format.opcode <= op_ldq_l))
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return (TRUE);
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/* Prefetches. */
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if (insn.mem_format.opcode == op_special) {
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/* Note: MB is treated as a store. */
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if ((insn.mem_format.displacement == (short)op_fetch) ||
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(insn.mem_format.displacement == (short)op_fetch_m))
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return (TRUE);
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}
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return (FALSE);
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}
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boolean_t
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db_inst_store(ins)
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int ins;
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{
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alpha_instruction insn;
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insn.bits = ins;
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/* Stores. */
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if (insn.mem_format.opcode == op_stw ||
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insn.mem_format.opcode == op_stb ||
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insn.mem_format.opcode == op_stq_u)
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return (TRUE);
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if ((insn.mem_format.opcode >= op_stf) &&
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(insn.mem_format.opcode <= op_stt))
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return (TRUE);
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if ((insn.mem_format.opcode >= op_stl) &&
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(insn.mem_format.opcode <= op_stq_c))
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return (TRUE);
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/* Barriers. */
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if (insn.mem_format.opcode == op_special) {
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if (insn.mem_format.displacement == op_mb)
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return (TRUE);
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}
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return (FALSE);
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}
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db_addr_t
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db_branch_taken(ins, pc, regs)
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int ins;
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db_addr_t pc;
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db_regs_t *regs;
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{
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alpha_instruction insn;
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db_addr_t newpc;
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insn.bits = ins;
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switch (insn.branch_format.opcode) {
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/*
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* Jump format: target PC is (contents of instruction's "RB") & ~3.
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*/
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|
case op_j:
|
|
newpc = db_register_value(regs, insn.jump_format.rs) & ~3;
|
|
break;
|
|
|
|
/*
|
|
* Branch format: target PC is
|
|
* (new PC) + (4 * sign-ext(displacement)).
|
|
*/
|
|
case op_br:
|
|
case op_fbeq:
|
|
case op_fblt:
|
|
case op_fble:
|
|
case op_bsr:
|
|
case op_fbne:
|
|
case op_fbge:
|
|
case op_fbgt:
|
|
case op_blbc:
|
|
case op_beq:
|
|
case op_blt:
|
|
case op_ble:
|
|
case op_blbs:
|
|
case op_bne:
|
|
case op_bge:
|
|
case op_bgt:
|
|
newpc = (insn.branch_format.displacement << 2) + (pc + 4);
|
|
break;
|
|
|
|
default:
|
|
printf("DDB: db_inst_branch_taken on non-branch!\n");
|
|
newpc = pc; /* XXX */
|
|
}
|
|
|
|
return (newpc);
|
|
}
|
|
|
|
void
|
|
db_show_mdpcpu(struct pcpu *pc)
|
|
{
|
|
|
|
db_printf("ipis = 0x%lx\n", pc->pc_pending_ipis);
|
|
db_printf("next ASN = %d\n", pc->pc_next_asn);
|
|
}
|