cea2b8b915
library:
o) Increase inline unit / large function growth limits for MIPS to accommodate
the needs of the Simple Executive, which uses a shocking amount of inlining.
o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and
the Octeon SoC.
o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific
board numbers, specifically to support the MR320.
o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd,
which improperly uses an evaluation board's board number and breaks board
detection at runtime. This board is sold by Portwell as the CAM-0100.
o) Add support for the RTC available on some Octeon boards.
o) Add support for the Octeon PCI bus. Note that rman_[sg]et_virtual for IO
ports can not work unless building for n64.
o) Clean up the CompactFlash driver to use Simple Executive macros and
structures where possible (it would be advisable to use the Simple Executive
API to set the PIO mode, too, but that is not done presently.) Also use
structures from FreeBSD's ATA layer rather than structures copied from
Linux.
o) Print available Octeon SoC features on boot.
o) Add support for the Octeon timecounter.
o) Use the Simple Executive's routines rather than local copies for doing reads
and writes to 64-bit addresses and use its macros for various device
addresses rather than using local copies.
o) Rename octeon_board_real to octeon_is_simulation to reduce differences with
Cavium-provided code originally written for Linux. Also make it use the
same simplified test that the Simple Executive and Linux both use rather
than our complex one.
o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus
to use normal interrupt allocation and setup routines.
o) Use the Simple Executive's bootmem facility to allocate physical memory for
the kernel, rather than assuming we know which addresses we can steal.
NB: This may reduce the amount of RAM the kernel reports you as having if
you are leaving large temporary allocations made by U-Boot allocated
when starting FreeBSD.
o) Add a port of the Cavium-provided Ethernet driver for Linux. This changes
Ethernet interface naming from rgmxN to octeN. The new driver has vast
improvements over the old one, both in performance and functionality, but
does still have some features which have not been ported entirely and there
may be unimplemented code that can be hit in everyday use. I will make
every effort to correct those as they are reported.
o) Support loading the kernel on non-contiguous cores.
o) Add very conservative support for harvesting randomness from the Octeon
random number device.
o) Turn SMP on by default.
o) Clean up the style of the Octeon kernel configurations a little and make
them compile with -march=octeon.
o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple
Executive.
o) Modify the Simple Executive to build on FreeBSD and to build without
executive-config.h or cvmx-config.h. In the future we may want to
revert part of these changes and supply executive-config.h and
cvmx-config.h and access to the options contained in those files via
kernel configuration files.
o) Modify the Simple Executive USB routines to support getting and setting
of the USB PID.
128 lines
3.1 KiB
C
128 lines
3.1 KiB
C
/*-
|
|
* Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*
|
|
* $FreeBSD$
|
|
*/
|
|
#include <sys/cdefs.h>
|
|
__FBSDID("$FreeBSD$");
|
|
|
|
#include <sys/param.h>
|
|
#include <sys/conf.h>
|
|
#include <sys/kernel.h>
|
|
#include <sys/smp.h>
|
|
#include <sys/systm.h>
|
|
|
|
#include <machine/hwfunc.h>
|
|
#include <machine/md_var.h>
|
|
#include <machine/smp.h>
|
|
|
|
#include <mips/cavium/octeon_pcmap_regs.h>
|
|
|
|
#include <contrib/octeon-sdk/cvmx.h>
|
|
#include <contrib/octeon-sdk/cvmx-interrupt.h>
|
|
|
|
/* XXX */
|
|
extern cvmx_bootinfo_t *octeon_bootinfo;
|
|
|
|
unsigned octeon_ap_boot = ~0;
|
|
|
|
void
|
|
platform_ipi_send(int cpuid)
|
|
{
|
|
cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
|
|
mips_wbflush();
|
|
}
|
|
|
|
void
|
|
platform_ipi_clear(void)
|
|
{
|
|
uint64_t action;
|
|
|
|
action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
|
|
KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
|
|
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
|
|
}
|
|
|
|
int
|
|
platform_ipi_intrnum(void)
|
|
{
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
platform_init_ap(int cpuid)
|
|
{
|
|
unsigned ipi_int_mask, clock_int_mask;
|
|
|
|
/*
|
|
* Set the exception base.
|
|
*/
|
|
mips_wr_ebase(0x80000000 | cpuid);
|
|
|
|
/*
|
|
* Clear any pending IPIs.
|
|
*/
|
|
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
|
|
|
|
/*
|
|
* Set up interrupts.
|
|
*/
|
|
octeon_ciu_reset();
|
|
|
|
/*
|
|
* Unmask the clock and ipi interrupts.
|
|
*/
|
|
clock_int_mask = hard_int_mask(5);
|
|
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
|
|
set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int_mask));
|
|
|
|
mips_wbflush();
|
|
}
|
|
|
|
int
|
|
platform_num_processors(void)
|
|
{
|
|
return (bitcount32(octeon_bootinfo->core_mask));
|
|
}
|
|
|
|
struct cpu_group *
|
|
platform_smp_topo(void)
|
|
{
|
|
return (smp_topo_none());
|
|
}
|
|
|
|
int
|
|
platform_start_ap(int cpuid)
|
|
{
|
|
if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0)
|
|
return (-1);
|
|
for (;;) {
|
|
DELAY(1000);
|
|
if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0)
|
|
return (0);
|
|
printf("Waiting for cpu%d to start\n", cpuid);
|
|
}
|
|
}
|