1031 lines
37 KiB
C++
1031 lines
37 KiB
C++
//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SplitAnalysis class as well as mutator functions for
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// live range splitting.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "SplitKit.h"
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#include "LiveRangeEdit.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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static cl::opt<bool>
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AllowSplit("spiller-splits-edges",
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cl::desc("Allow critical edge splitting during spilling"));
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//===----------------------------------------------------------------------===//
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// Split Analysis
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//===----------------------------------------------------------------------===//
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SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
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const LiveIntervals &lis,
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const MachineLoopInfo &mli)
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: MF(vrm.getMachineFunction()),
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VRM(vrm),
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LIS(lis),
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Loops(mli),
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TII(*MF.getTarget().getInstrInfo()),
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CurLI(0) {}
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void SplitAnalysis::clear() {
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UseSlots.clear();
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UsingInstrs.clear();
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UsingBlocks.clear();
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LiveBlocks.clear();
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CurLI = 0;
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}
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bool SplitAnalysis::canAnalyzeBranch(const MachineBasicBlock *MBB) {
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MachineBasicBlock *T, *F;
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SmallVector<MachineOperand, 4> Cond;
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return !TII.AnalyzeBranch(const_cast<MachineBasicBlock&>(*MBB), T, F, Cond);
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}
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/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
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void SplitAnalysis::analyzeUses() {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (MachineRegisterInfo::reg_iterator I = MRI.reg_begin(CurLI->reg),
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E = MRI.reg_end(); I != E; ++I) {
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MachineOperand &MO = I.getOperand();
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if (MO.isUse() && MO.isUndef())
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continue;
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MachineInstr *MI = MO.getParent();
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if (MI->isDebugValue() || !UsingInstrs.insert(MI))
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continue;
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UseSlots.push_back(LIS.getInstructionIndex(MI).getDefIndex());
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MachineBasicBlock *MBB = MI->getParent();
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UsingBlocks[MBB]++;
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}
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array_pod_sort(UseSlots.begin(), UseSlots.end());
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calcLiveBlockInfo();
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DEBUG(dbgs() << " counted "
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<< UsingInstrs.size() << " instrs, "
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<< UsingBlocks.size() << " blocks.\n");
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}
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/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
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/// where CurLI is live.
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void SplitAnalysis::calcLiveBlockInfo() {
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if (CurLI->empty())
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return;
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LiveInterval::const_iterator LVI = CurLI->begin();
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LiveInterval::const_iterator LVE = CurLI->end();
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SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
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UseI = UseSlots.begin();
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UseE = UseSlots.end();
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// Loop over basic blocks where CurLI is live.
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MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
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for (;;) {
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BlockInfo BI;
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BI.MBB = MFI;
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SlotIndex Start, Stop;
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tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
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// The last split point is the latest possible insertion point that dominates
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// all successor blocks. If interference reaches LastSplitPoint, it is not
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// possible to insert a split or reload that makes CurLI live in the
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// outgoing bundle.
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MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
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if (LSP == BI.MBB->end())
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BI.LastSplitPoint = Stop;
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else
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BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
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// LVI is the first live segment overlapping MBB.
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BI.LiveIn = LVI->start <= Start;
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if (!BI.LiveIn)
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BI.Def = LVI->start;
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// Find the first and last uses in the block.
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BI.Uses = hasUses(MFI);
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if (BI.Uses && UseI != UseE) {
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BI.FirstUse = *UseI;
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assert(BI.FirstUse >= Start);
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do ++UseI;
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while (UseI != UseE && *UseI < Stop);
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BI.LastUse = UseI[-1];
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assert(BI.LastUse < Stop);
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}
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// Look for gaps in the live range.
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bool hasGap = false;
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BI.LiveOut = true;
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while (LVI->end < Stop) {
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SlotIndex LastStop = LVI->end;
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if (++LVI == LVE || LVI->start >= Stop) {
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BI.Kill = LastStop;
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BI.LiveOut = false;
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break;
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}
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if (LastStop < LVI->start) {
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hasGap = true;
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BI.Kill = LastStop;
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BI.Def = LVI->start;
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}
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}
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// Don't set LiveThrough when the block has a gap.
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BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
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LiveBlocks.push_back(BI);
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// LVI is now at LVE or LVI->end >= Stop.
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if (LVI == LVE)
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break;
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// Live segment ends exactly at Stop. Move to the next segment.
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if (LVI->end == Stop && ++LVI == LVE)
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break;
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// Pick the next basic block.
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if (LVI->start < Stop)
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++MFI;
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else
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MFI = LIS.getMBBFromIndex(LVI->start);
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}
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}
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void SplitAnalysis::print(const BlockPtrSet &B, raw_ostream &OS) const {
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for (BlockPtrSet::const_iterator I = B.begin(), E = B.end(); I != E; ++I) {
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unsigned count = UsingBlocks.lookup(*I);
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OS << " BB#" << (*I)->getNumber();
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if (count)
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OS << '(' << count << ')';
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}
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}
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void SplitAnalysis::analyze(const LiveInterval *li) {
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clear();
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CurLI = li;
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analyzeUses();
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}
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//===----------------------------------------------------------------------===//
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// LiveIntervalMap
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//===----------------------------------------------------------------------===//
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// Work around the fact that the std::pair constructors are broken for pointer
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// pairs in some implementations. makeVV(x, 0) works.
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static inline std::pair<const VNInfo*, VNInfo*>
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makeVV(const VNInfo *a, VNInfo *b) {
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return std::make_pair(a, b);
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}
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void LiveIntervalMap::reset(LiveInterval *li) {
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LI = li;
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Values.clear();
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LiveOutCache.clear();
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}
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bool LiveIntervalMap::isComplexMapped(const VNInfo *ParentVNI) const {
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ValueMap::const_iterator i = Values.find(ParentVNI);
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return i != Values.end() && i->second == 0;
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}
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// defValue - Introduce a LI def for ParentVNI that could be later than
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// ParentVNI->def.
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VNInfo *LiveIntervalMap::defValue(const VNInfo *ParentVNI, SlotIndex Idx) {
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assert(LI && "call reset first");
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assert(ParentVNI && "Mapping NULL value");
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assert(Idx.isValid() && "Invalid SlotIndex");
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assert(ParentLI.getVNInfoAt(Idx) == ParentVNI && "Bad ParentVNI");
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// Create a new value.
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VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
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// Preserve the PHIDef bit.
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if (ParentVNI->isPHIDef() && Idx == ParentVNI->def)
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VNI->setIsPHIDef(true);
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// Use insert for lookup, so we can add missing values with a second lookup.
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std::pair<ValueMap::iterator,bool> InsP =
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Values.insert(makeVV(ParentVNI, Idx == ParentVNI->def ? VNI : 0));
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// This is now a complex def. Mark with a NULL in valueMap.
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if (!InsP.second)
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InsP.first->second = 0;
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return VNI;
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}
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// mapValue - Find the mapped value for ParentVNI at Idx.
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// Potentially create phi-def values.
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VNInfo *LiveIntervalMap::mapValue(const VNInfo *ParentVNI, SlotIndex Idx,
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bool *simple) {
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assert(LI && "call reset first");
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assert(ParentVNI && "Mapping NULL value");
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assert(Idx.isValid() && "Invalid SlotIndex");
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assert(ParentLI.getVNInfoAt(Idx) == ParentVNI && "Bad ParentVNI");
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// Use insert for lookup, so we can add missing values with a second lookup.
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std::pair<ValueMap::iterator,bool> InsP =
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Values.insert(makeVV(ParentVNI, 0));
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// This was an unknown value. Create a simple mapping.
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if (InsP.second) {
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if (simple) *simple = true;
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return InsP.first->second = LI->createValueCopy(ParentVNI,
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LIS.getVNInfoAllocator());
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}
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// This was a simple mapped value.
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if (InsP.first->second) {
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if (simple) *simple = true;
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return InsP.first->second;
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}
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// This is a complex mapped value. There may be multiple defs, and we may need
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// to create phi-defs.
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if (simple) *simple = false;
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MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
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assert(IdxMBB && "No MBB at Idx");
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// Is there a def in the same MBB we can extend?
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if (VNInfo *VNI = extendTo(IdxMBB, Idx))
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return VNI;
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// Now for the fun part. We know that ParentVNI potentially has multiple defs,
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// and we may need to create even more phi-defs to preserve VNInfo SSA form.
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// Perform a search for all predecessor blocks where we know the dominating
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// VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
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DEBUG(dbgs() << "\n Reaching defs for BB#" << IdxMBB->getNumber()
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<< " at " << Idx << " in " << *LI << '\n');
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// Blocks where LI should be live-in.
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SmallVector<MachineDomTreeNode*, 16> LiveIn;
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LiveIn.push_back(MDT[IdxMBB]);
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// Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
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for (unsigned i = 0; i != LiveIn.size(); ++i) {
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MachineBasicBlock *MBB = LiveIn[i]->getBlock();
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for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
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PE = MBB->pred_end(); PI != PE; ++PI) {
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MachineBasicBlock *Pred = *PI;
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// Is this a known live-out block?
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std::pair<LiveOutMap::iterator,bool> LOIP =
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LiveOutCache.insert(std::make_pair(Pred, LiveOutPair()));
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// Yes, we have been here before.
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if (!LOIP.second) {
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DEBUG(if (VNInfo *VNI = LOIP.first->second.first)
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dbgs() << " known valno #" << VNI->id
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<< " at BB#" << Pred->getNumber() << '\n');
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continue;
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}
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// Does Pred provide a live-out value?
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SlotIndex Last = LIS.getMBBEndIdx(Pred).getPrevSlot();
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if (VNInfo *VNI = extendTo(Pred, Last)) {
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MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(VNI->def);
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DEBUG(dbgs() << " found valno #" << VNI->id
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<< " from BB#" << DefMBB->getNumber()
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<< " at BB#" << Pred->getNumber() << '\n');
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LiveOutPair &LOP = LOIP.first->second;
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LOP.first = VNI;
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LOP.second = MDT[DefMBB];
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continue;
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}
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// No, we need a live-in value for Pred as well
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if (Pred != IdxMBB)
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LiveIn.push_back(MDT[Pred]);
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}
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}
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// We may need to add phi-def values to preserve the SSA form.
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// This is essentially the same iterative algorithm that SSAUpdater uses,
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// except we already have a dominator tree, so we don't have to recompute it.
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VNInfo *IdxVNI = 0;
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unsigned Changes;
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do {
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Changes = 0;
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DEBUG(dbgs() << " Iterating over " << LiveIn.size() << " blocks.\n");
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// Propagate live-out values down the dominator tree, inserting phi-defs when
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// necessary. Since LiveIn was created by a BFS, going backwards makes it more
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// likely for us to visit immediate dominators before their children.
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for (unsigned i = LiveIn.size(); i; --i) {
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MachineDomTreeNode *Node = LiveIn[i-1];
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MachineBasicBlock *MBB = Node->getBlock();
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MachineDomTreeNode *IDom = Node->getIDom();
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LiveOutPair IDomValue;
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// We need a live-in value to a block with no immediate dominator?
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// This is probably an unreachable block that has survived somehow.
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bool needPHI = !IDom;
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// Get the IDom live-out value.
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if (!needPHI) {
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LiveOutMap::iterator I = LiveOutCache.find(IDom->getBlock());
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if (I != LiveOutCache.end())
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IDomValue = I->second;
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else
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// If IDom is outside our set of live-out blocks, there must be new
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// defs, and we need a phi-def here.
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needPHI = true;
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}
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// IDom dominates all of our predecessors, but it may not be the immediate
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// dominator. Check if any of them have live-out values that are properly
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// dominated by IDom. If so, we need a phi-def here.
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if (!needPHI) {
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for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
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PE = MBB->pred_end(); PI != PE; ++PI) {
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LiveOutPair Value = LiveOutCache[*PI];
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if (!Value.first || Value.first == IDomValue.first)
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continue;
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// This predecessor is carrying something other than IDomValue.
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// It could be because IDomValue hasn't propagated yet, or it could be
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// because MBB is in the dominance frontier of that value.
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if (MDT.dominates(IDom, Value.second)) {
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needPHI = true;
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break;
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}
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}
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}
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// Create a phi-def if required.
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if (needPHI) {
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++Changes;
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SlotIndex Start = LIS.getMBBStartIdx(MBB);
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VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
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VNI->setIsPHIDef(true);
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DEBUG(dbgs() << " - BB#" << MBB->getNumber()
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<< " phi-def #" << VNI->id << " at " << Start << '\n');
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// We no longer need LI to be live-in.
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LiveIn.erase(LiveIn.begin()+(i-1));
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// Blocks in LiveIn are either IdxMBB, or have a value live-through.
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if (MBB == IdxMBB)
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IdxVNI = VNI;
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// Check if we need to update live-out info.
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LiveOutMap::iterator I = LiveOutCache.find(MBB);
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if (I == LiveOutCache.end() || I->second.second == Node) {
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// We already have a live-out defined in MBB, so this must be IdxMBB.
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assert(MBB == IdxMBB && "Adding phi-def to known live-out");
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LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
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} else {
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// This phi-def is also live-out, so color the whole block.
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LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
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I->second = LiveOutPair(VNI, Node);
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}
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} else if (IDomValue.first) {
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// No phi-def here. Remember incoming value for IdxMBB.
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if (MBB == IdxMBB)
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IdxVNI = IDomValue.first;
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// Propagate IDomValue if needed:
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// MBB is live-out and doesn't define its own value.
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LiveOutMap::iterator I = LiveOutCache.find(MBB);
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if (I != LiveOutCache.end() && I->second.second != Node &&
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I->second.first != IDomValue.first) {
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++Changes;
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I->second = IDomValue;
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DEBUG(dbgs() << " - BB#" << MBB->getNumber()
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<< " idom valno #" << IDomValue.first->id
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<< " from BB#" << IDom->getBlock()->getNumber() << '\n');
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}
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}
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}
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DEBUG(dbgs() << " - made " << Changes << " changes.\n");
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} while (Changes);
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assert(IdxVNI && "Didn't find value for Idx");
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#ifndef NDEBUG
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// Check the LiveOutCache invariants.
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for (LiveOutMap::iterator I = LiveOutCache.begin(), E = LiveOutCache.end();
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I != E; ++I) {
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assert(I->first && "Null MBB entry in cache");
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assert(I->second.first && "Null VNInfo in cache");
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assert(I->second.second && "Null DomTreeNode in cache");
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if (I->second.second->getBlock() == I->first)
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continue;
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for (MachineBasicBlock::pred_iterator PI = I->first->pred_begin(),
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PE = I->first->pred_end(); PI != PE; ++PI)
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assert(LiveOutCache.lookup(*PI) == I->second && "Bad invariant");
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}
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#endif
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// Since we went through the trouble of a full BFS visiting all reaching defs,
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// the values in LiveIn are now accurate. No more phi-defs are needed
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// for these blocks, so we can color the live ranges.
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// This makes the next mapValue call much faster.
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for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
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MachineBasicBlock *MBB = LiveIn[i]->getBlock();
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SlotIndex Start = LIS.getMBBStartIdx(MBB);
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VNInfo *VNI = LiveOutCache.lookup(MBB).first;
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// Anything in LiveIn other than IdxMBB is live-through.
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// In IdxMBB, we should stop at Idx unless the same value is live-out.
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if (MBB == IdxMBB && IdxVNI != VNI)
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LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
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else
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LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
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}
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return IdxVNI;
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}
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#ifndef NDEBUG
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void LiveIntervalMap::dumpCache() {
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for (LiveOutMap::iterator I = LiveOutCache.begin(), E = LiveOutCache.end();
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I != E; ++I) {
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assert(I->first && "Null MBB entry in cache");
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assert(I->second.first && "Null VNInfo in cache");
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assert(I->second.second && "Null DomTreeNode in cache");
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dbgs() << " cache: BB#" << I->first->getNumber()
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<< " has valno #" << I->second.first->id << " from BB#"
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<< I->second.second->getBlock()->getNumber() << ", preds";
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for (MachineBasicBlock::pred_iterator PI = I->first->pred_begin(),
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PE = I->first->pred_end(); PI != PE; ++PI)
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dbgs() << " BB#" << (*PI)->getNumber();
|
|
dbgs() << '\n';
|
|
}
|
|
dbgs() << " cache: " << LiveOutCache.size() << " entries.\n";
|
|
}
|
|
#endif
|
|
|
|
// extendTo - Find the last LI value defined in MBB at or before Idx. The
|
|
// ParentLI is assumed to be live at Idx. Extend the live range to Idx.
|
|
// Return the found VNInfo, or NULL.
|
|
VNInfo *LiveIntervalMap::extendTo(const MachineBasicBlock *MBB, SlotIndex Idx) {
|
|
assert(LI && "call reset first");
|
|
LiveInterval::iterator I = std::upper_bound(LI->begin(), LI->end(), Idx);
|
|
if (I == LI->begin())
|
|
return 0;
|
|
--I;
|
|
if (I->end <= LIS.getMBBStartIdx(MBB))
|
|
return 0;
|
|
if (I->end <= Idx)
|
|
I->end = Idx.getNextSlot();
|
|
return I->valno;
|
|
}
|
|
|
|
// addSimpleRange - Add a simple range from ParentLI to LI.
|
|
// ParentVNI must be live in the [Start;End) interval.
|
|
void LiveIntervalMap::addSimpleRange(SlotIndex Start, SlotIndex End,
|
|
const VNInfo *ParentVNI) {
|
|
assert(LI && "call reset first");
|
|
bool simple;
|
|
VNInfo *VNI = mapValue(ParentVNI, Start, &simple);
|
|
// A simple mapping is easy.
|
|
if (simple) {
|
|
LI->addRange(LiveRange(Start, End, VNI));
|
|
return;
|
|
}
|
|
|
|
// ParentVNI is a complex value. We must map per MBB.
|
|
MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
|
|
MachineFunction::iterator MBBE = LIS.getMBBFromIndex(End.getPrevSlot());
|
|
|
|
if (MBB == MBBE) {
|
|
LI->addRange(LiveRange(Start, End, VNI));
|
|
return;
|
|
}
|
|
|
|
// First block.
|
|
LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
|
|
|
|
// Run sequence of full blocks.
|
|
for (++MBB; MBB != MBBE; ++MBB) {
|
|
Start = LIS.getMBBStartIdx(MBB);
|
|
LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB),
|
|
mapValue(ParentVNI, Start)));
|
|
}
|
|
|
|
// Final block.
|
|
Start = LIS.getMBBStartIdx(MBB);
|
|
if (Start != End)
|
|
LI->addRange(LiveRange(Start, End, mapValue(ParentVNI, Start)));
|
|
}
|
|
|
|
/// addRange - Add live ranges to LI where [Start;End) intersects ParentLI.
|
|
/// All needed values whose def is not inside [Start;End) must be defined
|
|
/// beforehand so mapValue will work.
|
|
void LiveIntervalMap::addRange(SlotIndex Start, SlotIndex End) {
|
|
assert(LI && "call reset first");
|
|
LiveInterval::const_iterator B = ParentLI.begin(), E = ParentLI.end();
|
|
LiveInterval::const_iterator I = std::lower_bound(B, E, Start);
|
|
|
|
// Check if --I begins before Start and overlaps.
|
|
if (I != B) {
|
|
--I;
|
|
if (I->end > Start)
|
|
addSimpleRange(Start, std::min(End, I->end), I->valno);
|
|
++I;
|
|
}
|
|
|
|
// The remaining ranges begin after Start.
|
|
for (;I != E && I->start < End; ++I)
|
|
addSimpleRange(I->start, std::min(End, I->end), I->valno);
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Split Editor
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
|
|
SplitEditor::SplitEditor(SplitAnalysis &sa,
|
|
LiveIntervals &lis,
|
|
VirtRegMap &vrm,
|
|
MachineDominatorTree &mdt,
|
|
LiveRangeEdit &edit)
|
|
: SA(sa), LIS(lis), VRM(vrm),
|
|
MRI(vrm.getMachineFunction().getRegInfo()),
|
|
MDT(mdt),
|
|
TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
|
|
TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
|
|
Edit(edit),
|
|
OpenIdx(0),
|
|
RegAssign(Allocator)
|
|
{
|
|
// We don't need an AliasAnalysis since we will only be performing
|
|
// cheap-as-a-copy remats anyway.
|
|
Edit.anyRematerializable(LIS, TII, 0);
|
|
}
|
|
|
|
void SplitEditor::dump() const {
|
|
if (RegAssign.empty()) {
|
|
dbgs() << " empty\n";
|
|
return;
|
|
}
|
|
|
|
for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
|
|
dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
|
|
dbgs() << '\n';
|
|
}
|
|
|
|
VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
|
|
VNInfo *ParentVNI,
|
|
SlotIndex UseIdx,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) {
|
|
MachineInstr *CopyMI = 0;
|
|
SlotIndex Def;
|
|
LiveInterval *LI = Edit.get(RegIdx);
|
|
|
|
// Attempt cheap-as-a-copy rematerialization.
|
|
LiveRangeEdit::Remat RM(ParentVNI);
|
|
if (Edit.canRematerializeAt(RM, UseIdx, true, LIS)) {
|
|
Def = Edit.rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
|
|
} else {
|
|
// Can't remat, just insert a copy from parent.
|
|
CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
|
|
.addReg(Edit.getReg());
|
|
Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
|
|
}
|
|
|
|
// Define the value in Reg.
|
|
VNInfo *VNI = LIMappers[RegIdx].defValue(ParentVNI, Def);
|
|
VNI->setCopy(CopyMI);
|
|
|
|
// Add minimal liveness for the new value.
|
|
Edit.get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
|
|
return VNI;
|
|
}
|
|
|
|
/// Create a new virtual register and live interval.
|
|
void SplitEditor::openIntv() {
|
|
assert(!OpenIdx && "Previous LI not closed before openIntv");
|
|
|
|
// Create the complement as index 0.
|
|
if (Edit.empty()) {
|
|
Edit.create(MRI, LIS, VRM);
|
|
LIMappers.push_back(LiveIntervalMap(LIS, MDT, Edit.getParent()));
|
|
LIMappers.back().reset(Edit.get(0));
|
|
}
|
|
|
|
// Create the open interval.
|
|
OpenIdx = Edit.size();
|
|
Edit.create(MRI, LIS, VRM);
|
|
LIMappers.push_back(LiveIntervalMap(LIS, MDT, Edit.getParent()));
|
|
LIMappers[OpenIdx].reset(Edit.get(OpenIdx));
|
|
}
|
|
|
|
SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before enterIntvBefore");
|
|
DEBUG(dbgs() << " enterIntvBefore " << Idx);
|
|
Idx = Idx.getBaseIndex();
|
|
VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx;
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "enterIntvBefore called with invalid index");
|
|
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
|
|
assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
|
|
SlotIndex End = LIS.getMBBEndIdx(&MBB);
|
|
SlotIndex Last = End.getPrevSlot();
|
|
DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
|
|
VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Last);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return End;
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id);
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
|
|
LIS.getLastSplitPoint(Edit.getParent(), &MBB));
|
|
RegAssign.insert(VNI->def, End, OpenIdx);
|
|
DEBUG(dump());
|
|
return VNI->def;
|
|
}
|
|
|
|
/// useIntv - indicate that all instructions in MBB should use OpenLI.
|
|
void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
|
|
useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
|
|
}
|
|
|
|
void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
|
|
assert(OpenIdx && "openIntv not called before useIntv");
|
|
DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
DEBUG(dump());
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAfter");
|
|
DEBUG(dbgs() << " leaveIntvAfter " << Idx);
|
|
|
|
// The interval must be live beyond the instruction at Idx.
|
|
Idx = Idx.getBoundaryIndex();
|
|
VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx.getNextSlot();
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "No instruction at index");
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
|
|
llvm::next(MachineBasicBlock::iterator(MI)));
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvBefore");
|
|
DEBUG(dbgs() << " leaveIntvBefore " << Idx);
|
|
|
|
// The interval must be live into the instruction at Idx.
|
|
Idx = Idx.getBoundaryIndex();
|
|
VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Idx.getNextSlot();
|
|
}
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
assert(MI && "No instruction at index");
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
|
|
return VNI->def;
|
|
}
|
|
|
|
SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
|
|
SlotIndex Start = LIS.getMBBStartIdx(&MBB);
|
|
DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
|
|
|
|
VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Start);
|
|
if (!ParentVNI) {
|
|
DEBUG(dbgs() << ": not live\n");
|
|
return Start;
|
|
}
|
|
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
|
|
MBB.SkipPHIsAndLabels(MBB.begin()));
|
|
RegAssign.insert(Start, VNI->def, OpenIdx);
|
|
DEBUG(dump());
|
|
return VNI->def;
|
|
}
|
|
|
|
void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
|
|
assert(OpenIdx && "openIntv not called before overlapIntv");
|
|
assert(Edit.getParent().getVNInfoAt(Start) ==
|
|
Edit.getParent().getVNInfoAt(End.getPrevSlot()) &&
|
|
"Parent changes value in extended range");
|
|
assert(Edit.get(0)->getVNInfoAt(Start) && "Start must come from leaveIntv*");
|
|
assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
|
|
"Range cannot span basic blocks");
|
|
|
|
// Treat this as useIntv() for now. The complement interval will be extended
|
|
// as needed by mapValue().
|
|
DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
DEBUG(dump());
|
|
}
|
|
|
|
/// closeIntv - Indicate that we are done editing the currently open
|
|
/// LiveInterval, and ranges can be trimmed.
|
|
void SplitEditor::closeIntv() {
|
|
assert(OpenIdx && "openIntv not called before closeIntv");
|
|
OpenIdx = 0;
|
|
}
|
|
|
|
/// rewriteAssigned - Rewrite all uses of Edit.getReg().
|
|
void SplitEditor::rewriteAssigned() {
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit.getReg()),
|
|
RE = MRI.reg_end(); RI != RE;) {
|
|
MachineOperand &MO = RI.getOperand();
|
|
MachineInstr *MI = MO.getParent();
|
|
++RI;
|
|
// LiveDebugVariables should have handled all DBG_VALUE instructions.
|
|
if (MI->isDebugValue()) {
|
|
DEBUG(dbgs() << "Zapping " << *MI);
|
|
MO.setReg(0);
|
|
continue;
|
|
}
|
|
|
|
// <undef> operands don't really read the register, so just assign them to
|
|
// the complement.
|
|
if (MO.isUse() && MO.isUndef()) {
|
|
MO.setReg(Edit.get(0)->reg);
|
|
continue;
|
|
}
|
|
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI);
|
|
Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
|
|
|
|
// Rewrite to the mapped register at Idx.
|
|
unsigned RegIdx = RegAssign.lookup(Idx);
|
|
MO.setReg(Edit.get(RegIdx)->reg);
|
|
DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
|
|
<< Idx << ':' << RegIdx << '\t' << *MI);
|
|
|
|
// Extend liveness to Idx.
|
|
const VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
|
|
LIMappers[RegIdx].mapValue(ParentVNI, Idx);
|
|
}
|
|
}
|
|
|
|
/// rewriteSplit - Rewrite uses of Intvs[0] according to the ConEQ mapping.
|
|
void SplitEditor::rewriteComponents(const SmallVectorImpl<LiveInterval*> &Intvs,
|
|
const ConnectedVNInfoEqClasses &ConEq) {
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Intvs[0]->reg),
|
|
RE = MRI.reg_end(); RI != RE;) {
|
|
MachineOperand &MO = RI.getOperand();
|
|
MachineInstr *MI = MO.getParent();
|
|
++RI;
|
|
if (MO.isUse() && MO.isUndef())
|
|
continue;
|
|
// DBG_VALUE instructions should have been eliminated earlier.
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI);
|
|
Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
|
|
DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
|
|
<< Idx << ':');
|
|
const VNInfo *VNI = Intvs[0]->getVNInfoAt(Idx);
|
|
assert(VNI && "Interval not live at use.");
|
|
MO.setReg(Intvs[ConEq.getEqClass(VNI)]->reg);
|
|
DEBUG(dbgs() << VNI->id << '\t' << *MI);
|
|
}
|
|
}
|
|
|
|
void SplitEditor::finish() {
|
|
assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
|
|
|
|
// At this point, the live intervals in Edit contain VNInfos corresponding to
|
|
// the inserted copies.
|
|
|
|
// Add the original defs from the parent interval.
|
|
for (LiveInterval::const_vni_iterator I = Edit.getParent().vni_begin(),
|
|
E = Edit.getParent().vni_end(); I != E; ++I) {
|
|
const VNInfo *ParentVNI = *I;
|
|
if (ParentVNI->isUnused())
|
|
continue;
|
|
LiveIntervalMap &LIM = LIMappers[RegAssign.lookup(ParentVNI->def)];
|
|
VNInfo *VNI = LIM.defValue(ParentVNI, ParentVNI->def);
|
|
LIM.getLI()->addRange(LiveRange(ParentVNI->def,
|
|
ParentVNI->def.getNextSlot(), VNI));
|
|
// Mark all values as complex to force liveness computation.
|
|
// This should really only be necessary for remat victims, but we are lazy.
|
|
LIM.markComplexMapped(ParentVNI);
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
// Every new interval must have a def by now, otherwise the split is bogus.
|
|
for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I)
|
|
assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
|
|
#endif
|
|
|
|
// FIXME: Don't recompute the liveness of all values, infer it from the
|
|
// overlaps between the parent live interval and RegAssign.
|
|
// The mapValue algorithm is only necessary when:
|
|
// - The parent value maps to multiple defs, and new phis are needed, or
|
|
// - The value has been rematerialized before some uses, and we want to
|
|
// minimize the live range so it only reaches the remaining uses.
|
|
// All other values have simple liveness that can be computed from RegAssign
|
|
// and the parent live interval.
|
|
|
|
// Extend live ranges to be live-out for successor PHI values.
|
|
for (LiveInterval::const_vni_iterator I = Edit.getParent().vni_begin(),
|
|
E = Edit.getParent().vni_end(); I != E; ++I) {
|
|
const VNInfo *PHIVNI = *I;
|
|
if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
|
|
continue;
|
|
unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
|
|
LiveIntervalMap &LIM = LIMappers[RegIdx];
|
|
MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
|
|
DEBUG(dbgs() << " map phi in BB#" << MBB->getNumber() << '@' << PHIVNI->def
|
|
<< " -> " << RegIdx << '\n');
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
|
|
DEBUG(dbgs() << " pred BB#" << (*PI)->getNumber() << '@' << End);
|
|
// The predecessor may not have a live-out value. That is OK, like an
|
|
// undef PHI operand.
|
|
if (VNInfo *VNI = Edit.getParent().getVNInfoAt(End)) {
|
|
DEBUG(dbgs() << " has parent valno #" << VNI->id << " live out\n");
|
|
assert(RegAssign.lookup(End) == RegIdx &&
|
|
"Different register assignment in phi predecessor");
|
|
LIM.mapValue(VNI, End);
|
|
}
|
|
else
|
|
DEBUG(dbgs() << " is not live-out\n");
|
|
}
|
|
DEBUG(dbgs() << " " << *LIM.getLI() << '\n');
|
|
}
|
|
|
|
// Rewrite instructions.
|
|
rewriteAssigned();
|
|
|
|
// FIXME: Delete defs that were rematted everywhere.
|
|
|
|
// Get rid of unused values and set phi-kill flags.
|
|
for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I)
|
|
(*I)->RenumberValues(LIS);
|
|
|
|
// Now check if any registers were separated into multiple components.
|
|
ConnectedVNInfoEqClasses ConEQ(LIS);
|
|
for (unsigned i = 0, e = Edit.size(); i != e; ++i) {
|
|
// Don't use iterators, they are invalidated by create() below.
|
|
LiveInterval *li = Edit.get(i);
|
|
unsigned NumComp = ConEQ.Classify(li);
|
|
if (NumComp <= 1)
|
|
continue;
|
|
DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
|
|
SmallVector<LiveInterval*, 8> dups;
|
|
dups.push_back(li);
|
|
for (unsigned i = 1; i != NumComp; ++i)
|
|
dups.push_back(&Edit.create(MRI, LIS, VRM));
|
|
rewriteComponents(dups, ConEQ);
|
|
ConEQ.Distribute(&dups[0]);
|
|
}
|
|
|
|
// Calculate spill weight and allocation hints for new intervals.
|
|
VirtRegAuxInfo vrai(VRM.getMachineFunction(), LIS, SA.Loops);
|
|
for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I){
|
|
LiveInterval &li = **I;
|
|
vrai.CalculateRegClass(li.reg);
|
|
vrai.CalculateWeightAndHint(li);
|
|
DEBUG(dbgs() << " new interval " << MRI.getRegClass(li.reg)->getName()
|
|
<< ":" << li << '\n');
|
|
}
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Single Block Splitting
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
|
|
/// may be an advantage to split CurLI for the duration of the block.
|
|
bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
|
|
// If CurLI is local to one block, there is no point to splitting it.
|
|
if (LiveBlocks.size() <= 1)
|
|
return false;
|
|
// Add blocks with multiple uses.
|
|
for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
|
|
const BlockInfo &BI = LiveBlocks[i];
|
|
if (!BI.Uses)
|
|
continue;
|
|
unsigned Instrs = UsingBlocks.lookup(BI.MBB);
|
|
if (Instrs <= 1)
|
|
continue;
|
|
if (Instrs == 2 && BI.LiveIn && BI.LiveOut && !BI.LiveThrough)
|
|
continue;
|
|
Blocks.insert(BI.MBB);
|
|
}
|
|
return !Blocks.empty();
|
|
}
|
|
|
|
/// splitSingleBlocks - Split CurLI into a separate live interval inside each
|
|
/// basic block in Blocks.
|
|
void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
|
|
DEBUG(dbgs() << " splitSingleBlocks for " << Blocks.size() << " blocks.\n");
|
|
|
|
for (unsigned i = 0, e = SA.LiveBlocks.size(); i != e; ++i) {
|
|
const SplitAnalysis::BlockInfo &BI = SA.LiveBlocks[i];
|
|
if (!BI.Uses || !Blocks.count(BI.MBB))
|
|
continue;
|
|
|
|
openIntv();
|
|
SlotIndex SegStart = enterIntvBefore(BI.FirstUse);
|
|
if (BI.LastUse < BI.LastSplitPoint) {
|
|
useIntv(SegStart, leaveIntvAfter(BI.LastUse));
|
|
} else {
|
|
// THe last use os after tha last valid split point.
|
|
SlotIndex SegStop = leaveIntvBefore(BI.LastSplitPoint);
|
|
useIntv(SegStart, SegStop);
|
|
overlapIntv(SegStop, BI.LastUse);
|
|
}
|
|
closeIntv();
|
|
}
|
|
finish();
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Sub Block Splitting
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getBlockForInsideSplit - If CurLI is contained inside a single basic block,
|
|
/// and it wou pay to subdivide the interval inside that block, return it.
|
|
/// Otherwise return NULL. The returned block can be passed to
|
|
/// SplitEditor::splitInsideBlock.
|
|
const MachineBasicBlock *SplitAnalysis::getBlockForInsideSplit() {
|
|
// The interval must be exclusive to one block.
|
|
if (UsingBlocks.size() != 1)
|
|
return 0;
|
|
// Don't to this for less than 4 instructions. We want to be sure that
|
|
// splitting actually reduces the instruction count per interval.
|
|
if (UsingInstrs.size() < 4)
|
|
return 0;
|
|
return UsingBlocks.begin()->first;
|
|
}
|
|
|
|
/// splitInsideBlock - Split CurLI into multiple intervals inside MBB.
|
|
void SplitEditor::splitInsideBlock(const MachineBasicBlock *MBB) {
|
|
SmallVector<SlotIndex, 32> Uses;
|
|
Uses.reserve(SA.UsingInstrs.size());
|
|
for (SplitAnalysis::InstrPtrSet::const_iterator I = SA.UsingInstrs.begin(),
|
|
E = SA.UsingInstrs.end(); I != E; ++I)
|
|
if ((*I)->getParent() == MBB)
|
|
Uses.push_back(LIS.getInstructionIndex(*I));
|
|
DEBUG(dbgs() << " splitInsideBlock BB#" << MBB->getNumber() << " for "
|
|
<< Uses.size() << " instructions.\n");
|
|
assert(Uses.size() >= 3 && "Need at least 3 instructions");
|
|
array_pod_sort(Uses.begin(), Uses.end());
|
|
|
|
// Simple algorithm: Find the largest gap between uses as determined by slot
|
|
// indices. Create new intervals for instructions before the gap and after the
|
|
// gap.
|
|
unsigned bestPos = 0;
|
|
int bestGap = 0;
|
|
DEBUG(dbgs() << " dist (" << Uses[0]);
|
|
for (unsigned i = 1, e = Uses.size(); i != e; ++i) {
|
|
int g = Uses[i-1].distance(Uses[i]);
|
|
DEBUG(dbgs() << ") -" << g << "- (" << Uses[i]);
|
|
if (g > bestGap)
|
|
bestPos = i, bestGap = g;
|
|
}
|
|
DEBUG(dbgs() << "), best: -" << bestGap << "-\n");
|
|
|
|
// bestPos points to the first use after the best gap.
|
|
assert(bestPos > 0 && "Invalid gap");
|
|
|
|
// FIXME: Don't create intervals for low densities.
|
|
|
|
// First interval before the gap. Don't create single-instr intervals.
|
|
if (bestPos > 1) {
|
|
openIntv();
|
|
useIntv(enterIntvBefore(Uses.front()), leaveIntvAfter(Uses[bestPos-1]));
|
|
closeIntv();
|
|
}
|
|
|
|
// Second interval after the gap.
|
|
if (bestPos < Uses.size()-1) {
|
|
openIntv();
|
|
useIntv(enterIntvBefore(Uses[bestPos]), leaveIntvAfter(Uses.back()));
|
|
closeIntv();
|
|
}
|
|
|
|
finish();
|
|
}
|