548d35fd69
Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
TSO (TCP segmentation offload), RTH (Receive Traffic Hash).
Submitted by: Sriram Rapuru at Exar
MFC after: 2 weeks
387 lines
12 KiB
C
387 lines
12 KiB
C
/*-
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* Copyright(c) 2002-2011 Exar Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification are permitted provided the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Exar Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef VXGE_HAL_CHANNEL_H
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#define VXGE_HAL_CHANNEL_H
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__EXTERN_BEGIN_DECLS
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/*
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* __hal_dtr_h - Handle to the desriptor object used for nonoffload
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* send or receive. Generic handle which can be with txd or rxd
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*/
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typedef void *__hal_dtr_h;
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/*
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* enum __hal_channel_type_e - Enumerated channel types.
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* @VXGE_HAL_CHANNEL_TYPE_UNKNOWN: Unknown channel.
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* @VXGE_HAL_CHANNEL_TYPE_FIFO: fifo.
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* @VXGE_HAL_CHANNEL_TYPE_RING: ring.
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* @VXGE_HAL_CHANNEL_TYPE_SQ: Send Queue
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* @VXGE_HAL_CHANNEL_TYPE_SRQ: Receive Queue
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* @VXGE_HAL_CHANNEL_TYPE_CQRQ: Receive queue completion queue
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* @VXGE_HAL_CHANNEL_TYPE_UMQ: Up message queue
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* @VXGE_HAL_CHANNEL_TYPE_DMQ: Down message queue
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* @VXGE_HAL_CHANNEL_TYPE_MAX: Maximum number of HAL-supported
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* (and recognized) channel types. Currently: 7.
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*
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* Enumerated channel types. Currently there are only two link-layer
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* channels - X3100 fifo and X3100 ring. In the future the list will grow.
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*/
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typedef enum __hal_channel_type_e {
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VXGE_HAL_CHANNEL_TYPE_UNKNOWN = 0,
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VXGE_HAL_CHANNEL_TYPE_FIFO = 1,
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VXGE_HAL_CHANNEL_TYPE_RING = 2,
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VXGE_HAL_CHANNEL_TYPE_SEND_QUEUE = 3,
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VXGE_HAL_CHANNEL_TYPE_RECEIVE_QUEUE = 4,
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VXGE_HAL_CHANNEL_TYPE_COMPLETION_QUEUE = 5,
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VXGE_HAL_CHANNEL_TYPE_UP_MESSAGE_QUEUE = 6,
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VXGE_HAL_CHANNEL_TYPE_DOWN_MESSAGE_QUEUE = 7,
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VXGE_HAL_CHANNEL_TYPE_MAX = 8
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} __hal_channel_type_e;
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/*
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* __hal_dtr_item_t
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* @dtr: Pointer to the descriptors that contains the dma data
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* to/from the device.
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* @hal_priv: HAL Private data related to the dtr.
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* @uld_priv: ULD Private data related to the dtr.
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*/
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typedef struct __hal_dtr_item_t {
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void *dtr;
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void *hal_priv;
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void *uld_priv;
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u32 state;
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#define VXGE_HAL_CHANNEL_DTR_FREE 0
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#define VXGE_HAL_CHANNEL_DTR_RESERVED 1
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#define VXGE_HAL_CHANNEL_DTR_POSTED 2
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#define VXGE_HAL_CHANNEL_DTR_COMPLETED 3
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} __hal_dtr_item_t;
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/*
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* __hal_channel_t
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* @item: List item; used to maintain a list of open channels.
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* @type: Channel type. See vxge_hal_channel_type_e {}.
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* @devh: Device handle. HAL device object that contains _this_ channel.
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* @pdev: PCI Device object
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* @vph: Virtual path handle. Virtual Path Object that contains _this_ channel.
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* @length: Channel length. Currently allocated number of descriptors.
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* The channel length "grows" when more descriptors get allocated.
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* See _hal_mempool_grow.
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* @dtr_arr: Dtr array. Contains descriptors posted to the channel and their
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* private data.
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* Note that at any point in time @dtr_arr contains 3 types of
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* descriptors:
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* 1) posted but not yet consumed by X3100 device;
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* 2) consumed but not yet completed;
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* 3) completed.
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* @post_index: Post index. At any point in time points on the
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* position in the channel, which'll contain next to-be-posted
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* descriptor.
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* @compl_index: Completion index. At any point in time points on the
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* position in the channel, which will contain next
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* to-be-completed descriptor.
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* @reserve_index: Reserve index. At any point in time points on the
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* position in the channel, which will contain next
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* to-be-reserved descriptor.
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* @free_dtr_count: Number of dtrs free.
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* @posted_dtr_count: Number of dtrs posted
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* @post_lock: Lock to serialize multiple concurrent "posters" of descriptors
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* on the given channel.
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* @poll_bytes: Poll bytes.
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* @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize
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* to store per-operation control information.
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* @stats: Pointer to common statistics
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* @userdata: Per-channel opaque (void *) user-defined context, which may be
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* upper-layer driver object, ULP connection, etc.
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* Once channel is open, @userdata is passed back to user via
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* vxge_hal_channel_callback_f.
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*
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* HAL channel object.
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*
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* See also: vxge_hal_channel_type_e {}, vxge_hal_channel_flag_e
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*/
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typedef struct __hal_channel_t {
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vxge_list_t item;
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__hal_channel_type_e type;
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vxge_hal_device_h devh;
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pci_dev_h pdev;
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vxge_hal_vpath_h vph;
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u32 length;
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u32 is_initd;
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__hal_dtr_item_t *dtr_arr;
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u32 compl_index __vxge_os_attr_cacheline_aligned;
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u32 reserve_index __vxge_os_attr_cacheline_aligned;
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spinlock_t post_lock;
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u32 poll_bytes;
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u32 per_dtr_space;
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vxge_hal_vpath_stats_sw_common_info_t *stats;
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void *userdata;
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} __hal_channel_t __vxge_os_attr_cacheline_aligned;
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#define __hal_channel_is_posted_dtr(channel, index) \
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((channel)->dtr_arr[index].state == VXGE_HAL_CHANNEL_DTR_POSTED)
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#define __hal_channel_for_each_posted_dtr(channel, dtrh, index) \
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for (index = (channel)->compl_index,\
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dtrh = (channel)->dtr_arr[index].dtr; \
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(index < (channel)->reserve_index) && \
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((channel)->dtr_arr[index].state == VXGE_HAL_CHANNEL_DTR_POSTED); \
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index = (++index == (channel)->length)? 0 : index, \
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dtrh = (channel)->dtr_arr[index].dtr)
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#define __hal_channel_for_each_dtr(channel, dtrh, index) \
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for (index = 0, dtrh = (channel)->dtr_arr[index].dtr; \
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index < (channel)->length; \
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dtrh = ((++index == (channel)->length)? 0 : \
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(channel)->dtr_arr[index].dtr))
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#define __hal_channel_free_dtr_count(channel) \
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(((channel)->reserve_index < (channel)->compl_index) ? \
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((channel)->compl_index - (channel)->reserve_index) : \
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(((channel)->length - (channel)->reserve_index) + \
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(channel)->reserve_index))
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/* ========================== CHANNEL PRIVATE API ========================= */
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__hal_channel_t *
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vxge_hal_channel_allocate(
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vxge_hal_device_h devh,
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vxge_hal_vpath_h vph,
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__hal_channel_type_e type,
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u32 length,
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u32 per_dtr_space,
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void *userdata);
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void
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vxge_hal_channel_free(
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__hal_channel_t *channel);
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vxge_hal_status_e
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vxge_hal_channel_initialize(
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__hal_channel_t *channel);
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vxge_hal_status_e
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__hal_channel_reset(
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__hal_channel_t *channel);
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void
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vxge_hal_channel_terminate(
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__hal_channel_t *channel);
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void
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__hal_channel_init_pending_list(
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vxge_hal_device_h devh);
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void
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__hal_channel_insert_pending_list(
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__hal_channel_t * channel);
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void
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__hal_channel_process_pending_list(
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vxge_hal_device_h devhv);
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void
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__hal_channel_destroy_pending_list(
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vxge_hal_device_h devh);
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#if defined(VXGE_DEBUG_FP) && (VXGE_DEBUG_FP & VXGE_DEBUG_FP_CHANNEL)
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#define __HAL_STATIC_CHANNEL
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#define __HAL_INLINE_CHANNEL
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#else /* VXGE_FASTPATH_EXTERN */
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#define __HAL_STATIC_CHANNEL static
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#define __HAL_INLINE_CHANNEL inline
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#endif /* VXGE_FASTPATH_INLINE */
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/* ========================== CHANNEL Fast Path API ========================= */
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/*
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* __hal_channel_dtr_reserve- Reserve a dtr from the channel
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* @channelh: Channel
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* @dtrh: Buffer to return the DTR pointer
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*
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* Reserve a dtr from the reserve array.
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*
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL vxge_hal_status_e
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/* LINTED */
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__hal_channel_dtr_reserve(__hal_channel_t *channel, __hal_dtr_h *dtrh)
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{
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vxge_hal_status_e status = VXGE_HAL_INF_OUT_OF_DESCRIPTORS;
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*dtrh = NULL;
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if (channel->dtr_arr[channel->reserve_index].state ==
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VXGE_HAL_CHANNEL_DTR_FREE) {
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*dtrh = channel->dtr_arr[channel->reserve_index].dtr;
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channel->dtr_arr[channel->reserve_index].state =
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VXGE_HAL_CHANNEL_DTR_RESERVED;
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if (++channel->reserve_index == channel->length)
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channel->reserve_index = 0;
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status = VXGE_HAL_OK;
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} else {
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#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
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__hal_device_t *hldev = (__hal_device_t *) channel->devh;
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vxge_hal_info_log_channel("channel %d is full!", channel->type);
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#endif
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channel->stats->full_cnt++;
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}
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return (status);
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}
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/*
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* __hal_channel_dtr_restore - Restores a dtr to the channel
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* @channelh: Channel
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* @dtr: DTR pointer
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*
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* Returns a dtr back to reserve array.
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*
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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/* LINTED */
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__hal_channel_dtr_restore(__hal_channel_t *channel, __hal_dtr_h dtrh)
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{
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u32 dtr_index;
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/*
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* restore a previously allocated dtrh at current offset and update
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* the available reserve length accordingly. If dtrh is null just
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* update the reserve length, only
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*/
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if (channel->reserve_index == 0)
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dtr_index = channel->length;
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else
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dtr_index = channel->reserve_index - 1;
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if ((channel->dtr_arr[dtr_index].dtr == dtrh)) {
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channel->reserve_index = dtr_index;
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channel->dtr_arr[dtr_index].state = VXGE_HAL_CHANNEL_DTR_FREE;
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#if (VXGE_COMPONENT_HAL_CHANNEL & VXGE_DEBUG_MODULE_MASK)
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__hal_device_t *hldev = (__hal_device_t *) channel->devh;
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vxge_hal_info_log_channel("dtrh 0x"VXGE_OS_STXFMT" \
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restored for " "channel %d at reserve index %d, ",
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(ptr_t) dtrh, channel->type,
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channel->reserve_index);
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#endif
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}
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}
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/*
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* __hal_channel_dtr_post - Post a dtr to the channel
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* @channelh: Channel
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* @dtr: DTR pointer
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*
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* Posts a dtr to work array.
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*
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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/* LINTED */
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__hal_channel_dtr_post(__hal_channel_t *channel, u32 dtr_index)
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{
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channel->dtr_arr[dtr_index].state =
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VXGE_HAL_CHANNEL_DTR_POSTED;
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}
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/*
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* __hal_channel_dtr_try_complete - Returns next completed dtr
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* @channelh: Channel
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* @dtr: Buffer to return the next completed DTR pointer
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*
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* Returns the next completed dtr with out removing it from work array
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*
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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/* LINTED */
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__hal_channel_dtr_try_complete(__hal_channel_t *channel, __hal_dtr_h *dtrh)
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{
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vxge_assert(channel->dtr_arr);
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vxge_assert(channel->compl_index < channel->length);
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if (channel->dtr_arr[channel->compl_index].state ==
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VXGE_HAL_CHANNEL_DTR_POSTED)
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*dtrh = channel->dtr_arr[channel->compl_index].dtr;
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else
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*dtrh = NULL;
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}
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/*
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* __hal_channel_dtr_complete - Removes next completed dtr from the work array
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* @channelh: Channel
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*
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* Removes the next completed dtr from work array
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*
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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/* LINTED */
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__hal_channel_dtr_complete(__hal_channel_t *channel)
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{
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channel->dtr_arr[channel->compl_index].state =
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VXGE_HAL_CHANNEL_DTR_COMPLETED;
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if (++channel->compl_index == channel->length)
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channel->compl_index = 0;
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channel->stats->total_compl_cnt++;
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}
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/*
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* __hal_channel_dtr_free - Frees a dtr
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* @channelh: Channel
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* @index: Index of DTR
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*
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* Returns the dtr to free array
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*
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*/
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__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
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/* LINTED */
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__hal_channel_dtr_free(__hal_channel_t *channel, u32 dtr_index)
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{
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channel->dtr_arr[dtr_index].state =
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VXGE_HAL_CHANNEL_DTR_FREE;
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}
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__EXTERN_END_DECLS
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#endif /* VXGE_HAL_CHANNEL_H */
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