4dbbaf2021
the "power down" watchdog used by the ROM boot code is still active when the regular watchdog is activated, turn off the power-down watchdog. This adds support for the "fsl,ext-reset-output" FDT property. When present, that property indicates that a chip reset is accomplished by asserting the WDOG1_B external signal, which is supposed to trigger some external component such as a PMIC to ready the hardware for reset (for example, adjusting voltages from idle to full-power levels), and assert the POR signal to SoC when ready. To guard against misconfiguation leading to a non-rebootable system, the external reset signal is backstopped by code that asserts a normal internal chip reset if nothing responds to the external reset signal within one second.
133 lines
4.5 KiB
C
133 lines
4.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/reboot.h>
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#include <sys/devmap.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/machdep.h>
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#include <arm/freescale/imx/imx_machdep.h>
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#include <arm/freescale/imx/imx_wdogreg.h>
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SYSCTL_NODE(_hw, OID_AUTO, imx, CTLFLAG_RW, NULL, "i.MX container");
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static int last_reset_status;
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SYSCTL_UINT(_hw_imx, OID_AUTO, last_reset_status, CTLFLAG_RD,
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&last_reset_status, 0, "Last reset status register");
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SYSCTL_STRING(_hw_imx, OID_AUTO, last_reset_reason, CTLFLAG_RD,
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"unknown", 0, "Last reset reason");
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/*
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* This code which manipulates the watchdog hardware is here to implement
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* cpu_reset() because the watchdog is the only way for software to reset the
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* chip. Why here and not in imx_wdog.c? Because there's no requirement that
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* the watchdog driver be compiled in, but it's nice to be able to reboot even
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* if it's not.
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*/
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void
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imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr)
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{
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volatile uint16_t cr, *pcr;
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if ((pcr = devmap_ptov(wdcr_physaddr, sizeof(*pcr))) == NULL) {
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printf("imx_wdog_cpu_reset(): "
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"cannot find control register... locking up now.");
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for (;;)
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cpu_spinwait();
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}
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cr = *pcr;
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/*
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* If the watchdog hardware has been set up to trigger an external reset
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* signal on watchdog timeout, then we do software-requested rebooting
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* the same way, by asserting the external reset signal.
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*
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* Asserting external reset is supposed to result in some external
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* component asserting the POR pin on the SoC, possibly after adjusting
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* and stabilizing system voltages, or taking other system-wide reset
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* actions. Just in case there is some kind of misconfiguration, we
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* hang out and do nothing for a full second, then continue on into
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* the code to assert a software reset as well.
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*/
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if (cr & WDOG_CR_WDT) {
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cr &= ~WDOG_CR_WDA; /* Assert active-low ext reset bit. */
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*pcr = cr;
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DELAY(1000000);
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printf("imx_wdog_cpu_reset(): "
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"External reset failed, trying internal cpu-reset\n");
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DELAY(10000); /* Time for printf to appear */
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}
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/*
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* Imx6 erratum ERR004346 says the SRS bit has to be cleared twice
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* within the same cycle of the 32khz clock to reliably trigger the
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* reset. Writing it 3 times in a row ensures at least 2 of the writes
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* happen in the same 32k clock cycle.
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*/
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cr &= ~WDOG_CR_SRS; /* Assert active-low software reset bit. */
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*pcr = cr;
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*pcr = cr;
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*pcr = cr;
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/* Reset happens on the next tick of the 32khz clock, wait for it. */
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for (;;)
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cpu_spinwait();
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}
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void
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imx_wdog_init_last_reset(vm_offset_t wdsr_phys)
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{
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volatile uint16_t * psr;
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if ((psr = devmap_ptov(wdsr_phys, sizeof(*psr))) == NULL)
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return;
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last_reset_status = *psr;
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if (last_reset_status & WDOG_RSR_SFTW) {
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sysctl___hw_imx_last_reset_reason.oid_arg1 = "SoftwareReset";
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} else if (last_reset_status & WDOG_RSR_TOUT) {
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sysctl___hw_imx_last_reset_reason.oid_arg1 = "WatchdogTimeout";
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} else if (last_reset_status & WDOG_RSR_POR) {
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sysctl___hw_imx_last_reset_reason.oid_arg1 = "PowerOnReset";
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}
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}
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