718cf2ccb9
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244 lines
8.2 KiB
C
244 lines
8.2 KiB
C
/* $FreeBSD$ */
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-NetBSD
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*
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ken Hornstein and John Kohl.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer
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* chip, used on Gravis UltraSound MAX cards.
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*
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* Block diagram:
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* +----------------------------------------------------+
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* | |
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* | +----------------------------------------------+ |
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* | |mixed in +-+ | |
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* | +------------>--| | | |
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* | mic in | | | |
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* Mic --+-->| --------- GAIN ->-| | | |
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* | | AUX 1 in |M| | |
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* GF1 --)-->| -------------+-->-|U| | |
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* | | Line in | |X|---- GAIN ----------+ | |
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* Line --)-->| ---------+---)-->-| | | | |
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* | | | | | | | | |
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* | | | | +-+ ADC | |
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* | | | | | | |
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* | | | | | | |
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* | | | +--- L/M --\ | | | AMP-->
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* | | | \ | | | |
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* | | | \ | | | |
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* | | +---- L/M -------O-->--+--------)-------+-|--+-> line
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* | | mono in /| | | |
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* +---|-->------------ L/M -----/ | | | |
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* | AUX 2 in | | | |
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* CD --------|-->------------ L/M -------+ L/M | |
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* | | v |
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* | | | |
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* | DAC | |
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* | | | |
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* +----------------------------------------------------+
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* | |
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* | |
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* v v
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* Pc BUS (DISK) ???
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*
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* Documentation for this chip can be found at:
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* http://www.cirrus.com/products/overviews/cs4231.html
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*/
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/*
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* This file was merged from two header files.(ad1848reg.h and cs4231reg.h)
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* And the suffix AD1848 and SP was changed to CS4231 and CS respectively.
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*/
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/* CS4231 direct registers */
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#define CS4231_IADDR 0x00
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#define CS4231_IDATA 0x01
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#define CS4231_STATUS 0x02
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#define CS4231_PIO 0x03
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/* Index address register */
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#define CS_IN_INIT 0x80
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#define MODE_CHANGE_ENABLE 0x40
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#define TRANSFER_DISABLE 0x20
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#define ADDRESS_MASK 0xe0
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/* Status bits */
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#define INTERRUPT_STATUS 0x01
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#define PLAYBACK_READY 0x02
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#define PLAYBACK_LEFT 0x04
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/* pbright is not left */
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#define PLAYBACK_UPPER 0x08
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/* bplower is not upper */
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#define SAMPLE_ERROR 0x10
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#define CAPTURE_READY 0x20
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#define CAPTURE_LEFT 0x40
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/* cpright is not left */
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#define CAPTURE_UPPER 0x80
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/* cplower is not upper */
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/* CS4231 indirect mapped registers */
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#define CS_LEFT_INPUT_CONTROL 0x00
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#define CS_RIGHT_INPUT_CONTROL 0x01
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#define CS_LEFT_AUX1_CONTROL 0x02
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#define CS_RIGHT_AUX1_CONTROL 0x03
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#define CS_LEFT_AUX2_CONTROL 0x04
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#define CS_RIGHT_AUX2_CONTROL 0x05
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#define CS_LEFT_OUTPUT_CONTROL 0x06
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#define CS_RIGHT_OUTPUT_CONTROL 0x07
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#define CS_CLOCK_DATA_FORMAT 0x08
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#define CS_INTERFACE_CONFIG 0x09
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#define CS_PIN_CONTROL 0x0a
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#define CS_TEST_AND_INIT 0x0b
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#define CS_MISC_INFO 0x0c
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#define CS_DIGITAL_MIX 0x0d
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#define CS_UPPER_BASE_COUNT 0x0e
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#define CS_LOWER_BASE_COUNT 0x0f
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/* CS4231/AD1845 mode2 registers; added to AD1848 registers */
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#define CS_ALT_FEATURE1 0x10
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#define CS_ALT_FEATURE2 0x11
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#define CS_LEFT_LINE_CONTROL 0x12
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#define CS_RIGHT_LINE_CONTROL 0x13
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#define CS_TIMER_LOW 0x14
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#define CS_TIMER_HIGH 0x15
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#define CS_UPPER_FREQUENCY_SEL 0x16
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#define CS_LOWER_FREQUENCY_SEL 0x17
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#define CS_IRQ_STATUS 0x18
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#define CS_VERSION_ID 0x19
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#define CS_MONO_IO_CONTROL 0x1a
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#define CS_POWERDOWN_CONTROL 0x1b
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#define CS_REC_FORMAT 0x1c
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#define CS_XTAL_SELECT 0x1d
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#define CS_UPPER_REC_CNT 0x1e
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#define CS_LOWER_REC_CNT 0x1f
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#define CS_REG_NONE 0xff
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#define CS_IN_MASK 0x2f
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#define CS_IN_LINE 0x00
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#define CS_IN_AUX1 0x40
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#define CS_IN_MIC 0x80
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#define CS_IN_DAC 0xc0
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#define CS_MIC_GAIN_ENABLE 0x20
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#define CS_IN_GAIN_MASK 0xf0
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/* ADC input control - registers I0 (channel 1,left); I1 (channel 1,right) */
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#define ADC_INPUT_ATTEN_BITS 0x0f
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#define ADC_INPUT_GAIN_ENABLE 0x20
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/* Aux input control - registers I2 (channel 1,left); I3 (channel 1,right)
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I4 (channel 2,left); I5 (channel 2,right) */
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#define AUX_INPUT_ATTEN_BITS 0x1f
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#define AUX_INPUT_ATTEN_MASK 0xe0
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#define AUX_INPUT_MUTE 0x80
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/* Output bits - registers I6,I7*/
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#define OUTPUT_MUTE 0x80
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#define OUTPUT_ATTEN_BITS 0x3f
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#define OUTPUT_ATTEN_MASK (~OUTPUT_ATTEN_BITS & 0xff)
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/* Clock and Data format reg bits (some also Capture Data format) - reg I8 */
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#define CS_CLOCK_DATA_FORMAT_MASK 0x0f
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#define CLOCK_XTAL1 0x00
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#define CLOCK_XTAL2 0x01
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#define CLOCK_FREQ_MASK 0xf1
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#define CS_AFMT_STEREO 0x10
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#define CS_AFMT_U8 0x00
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#define CS_AFMT_MU_LAW 0x20
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#define CS_AFMT_S16_LE 0x40
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#define CS_AFMT_A_LAW 0x60
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#define CS_AFMT_IMA_ADPCM 0xa0
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#define CS_AFMT_S16_BE 0xc0
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/* Interface Configuration reg bits - register I9 */
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#define PLAYBACK_ENABLE 0x01
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#define CAPTURE_ENABLE 0x02
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#define DUAL_DMA 0x00
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#define SINGLE_DMA 0x04
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#define AUTO_CAL_ENABLE 0x08
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#define PLAYBACK_PIO_ENABLE 0x40
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#define CAPTURE_PIO_ENABLE 0x80
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/* Pin control bits - register I10 */
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#define INTERRUPT_ENABLE 0x02
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#define XCTL0_ENABLE 0x40
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#define XCTL1_ENABLE 0x80
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/* Test and init reg bits - register I11 (read-only) */
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#define OVERRANGE_LEFT_MASK 0xfc
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#define OVERRANGE_RIGHT_MASK 0xf3
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#define DATA_REQUEST_STATUS 0x10
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#define AUTO_CAL_IN_PROG 0x20
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#define PLAYBACK_UNDERRUN 0x40
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#define CAPTURE_OVERRUN 0x80
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/* Miscellaneous Control reg bits - register I12 */
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#define CS_ID_MASK 0x70
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#define CS_MODE2 0x40
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#define CS_CODEC_ID_MASK 0x0f
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/* Digital Mix Control reg bits - register I13 */
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#define DIGITAL_MIX1_ENABLE 0x01
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#define MIX_ATTEN_MASK 0x03
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/* Alternate Feature Enable I - register I16 */
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#define CS_DAC_ZERO 0x01
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#define CS_PMC_ENABLE 0x10
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#define CS_CMC_ENABLE 0x20
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#define CS_OUTPUT_LVL 0x80
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/* Alternate Feature Enable II - register I17 */
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#define CS_HPF_ENABLE 0x01
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#define DUAL_XTAL_ENABLE 0x02
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/* alternate feature status(I24) */
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#define CS_AFS_TI 0x40 /* timer interrupt */
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#define CS_AFS_CI 0x20 /* capture interrupt */
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#define CS_AFS_PI 0x10 /* playback interrupt */
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#define CS_AFS_CU 0x08 /* capture underrun */
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#define CS_AFS_CO 0x04 /* capture overrun */
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#define CS_AFS_PO 0x02 /* playback overrun */
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#define CS_AFS_PU 0x01 /* playback underrun */
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/* Version - register I25 */
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#define CS_VERSION_NUMBER 0xe0
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#define CS_VERSION_CHIPID 0x07
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/* Miscellaneous Control reg bits */
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#define CS_MODE2 0x40
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#define MONO_INPUT_ATTEN_BITS 0x0f
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#define MONO_INPUT_ATTEN_MASK 0xf0
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#define MONO_OUTPUT_MUTE 0x40
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#define MONO_INPUT_MUTE 0x80
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#define MONO_INPUT_MUTE_MASK 0x7f
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#define LINE_INPUT_ATTEN_BITS 0x1f
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#define LINE_INPUT_ATTEN_MASK 0xe0
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#define LINE_INPUT_MUTE 0x80
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#define LINE_INPUT_MUTE_MASK 0x7f
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