d0036d6ebc
of I/O in 1.5. It looks like I got it right only for some of the cases. Instead, allow ISA addresses as a special case. Most PCI bridges decode this range. I need to investigate PCI bridges better to know if this is always true or not, but for now assume that it is since that seems to be the most common case. # We need to allocate addresses better for the pccard stuff... Submitted by: phk, mitsunaga-san
413 lines
13 KiB
C
413 lines
13 KiB
C
/*-
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* Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
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* Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* PCI:PCI bridge support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <machine/resource.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include "pcib_if.h"
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#include "opt_pci.h"
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/*
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* Bridge-specific data.
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*/
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struct pcib_softc
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{
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device_t dev;
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u_int16_t command; /* command register */
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u_int8_t secbus; /* secondary bus number */
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u_int8_t subbus; /* subordinate bus number */
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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pci_addr_t membase; /* base address of memory window */
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pci_addr_t memlimit; /* topmost address of memory window */
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u_int32_t iobase; /* base address of port window */
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u_int32_t iolimit; /* topmost address of port window */
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u_int16_t secstat; /* secondary bus status register */
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u_int16_t bridgectl; /* bridge control register */
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u_int8_t seclat; /* secondary bus latency timer */
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};
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static int pcib_probe(device_t dev);
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static int pcib_attach(device_t dev);
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static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
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static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
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static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags);
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static int pcib_maxslots(device_t dev);
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static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
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static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width);
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static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
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static device_method_t pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pcib_probe),
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DEVMETHOD(device_attach, pcib_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, pcib_read_ivar),
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DEVMETHOD(bus_write_ivar, pcib_write_ivar),
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DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pcib_maxslots),
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DEVMETHOD(pcib_read_config, pcib_read_config),
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DEVMETHOD(pcib_write_config, pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
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{ 0, 0 }
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};
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static driver_t pcib_driver = {
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"pcib",
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pcib_methods,
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sizeof(struct pcib_softc),
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};
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static devclass_t pcib_devclass;
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DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
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/*
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* Generic device interface
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*/
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static int
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pcib_probe(device_t dev)
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{
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if ((pci_get_class(dev) == PCIC_BRIDGE) &&
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(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
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device_set_desc(dev, "PCI-PCI bridge");
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return(-10000);
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}
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return(ENXIO);
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}
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static int
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pcib_attach(device_t dev)
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{
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struct pcib_softc *sc;
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device_t child;
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u_int8_t iolow;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/*
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* Get current bridge configuration.
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*/
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sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
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sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
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sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
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sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
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sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
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sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
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/*
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* Determine current I/O decode.
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*/
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if (sc->command & PCIM_CMD_PORTEN) {
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iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
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if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
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sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
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pci_read_config(dev, PCIR_IOBASEL_1, 1));
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} else {
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sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
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}
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iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
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if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
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sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
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pci_read_config(dev, PCIR_IOLIMITL_1, 1));
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} else {
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sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
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}
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}
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/*
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* Determine current memory decode.
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*/
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if (sc->command & PCIM_CMD_MEMEN) {
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sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
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sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
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sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
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pci_read_config(dev, PCIR_PMBASEL_1, 2));
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sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
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pci_read_config(dev, PCIR_PMLIMITL_1, 2));
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}
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/*
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* Quirk handling.
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*/
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switch (pci_get_devid(dev)) {
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case 0x12258086: /* Intel 82454KX/GX (Orion) */
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{
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u_int8_t supbus;
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supbus = pci_read_config(dev, 0x41, 1);
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if (supbus != 0xff) {
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sc->secbus = supbus + 1;
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sc->subbus = supbus + 1;
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}
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}
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break;
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}
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if (bootverbose) {
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device_printf(dev, " secondary bus %d\n", sc->secbus);
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device_printf(dev, " subordinate bus %d\n", sc->subbus);
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device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
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device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
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device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
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}
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/*
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* XXX If the secondary bus number is zero, we should assign a bus number
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* since the BIOS hasn't, then initialise the bridge.
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*/
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/*
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* XXX If the subordinate bus number is less than the secondary bus number,
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* we should pick a better value. One sensible alternative would be to
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* pick 255; the only tradeoff here is that configuration transactions
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* would be more widely routed than absolutely necessary.
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*/
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if (sc->secbus != 0) {
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child = device_add_child(dev, "pci", -1);
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if (child != NULL)
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return(bus_generic_attach(dev));
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}
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/* no secondary bus; we should have fixed this */
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return(0);
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}
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static int
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pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct pcib_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = sc->secbus;
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return(0);
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}
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return(ENOENT);
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}
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static int
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pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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{
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struct pcib_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->secbus = value;
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break;
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}
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return(ENOENT);
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}
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/*
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* Is this a decoded ISA I/O port address? Note, we need to do the mask that
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* we do below because of the ISA alias addresses. I'm not 100% sure that
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* this is correct.
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*/
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static int
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pcib_is_isa_io(u_long start)
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{
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if ((start & 0xfffUL) > 0x3ffUL)
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return (0);
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return (1);
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}
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/*
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* Is this a decoded ISA memory address?
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*/
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static int
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pcib_is_isa_mem(u_long start)
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{
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if (start > 0xfffffUL)
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return (0);
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return (1);
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}
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/*
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* We have to trap resource allocation requests and ensure that the bridge
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* is set up to, or capable of handling them.
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*/
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static struct resource *
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pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct pcib_softc *sc = device_get_softc(dev);
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/*
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* If this is a "default" allocation against this rid, we can't work
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* out where it's coming from (we should actually never see these) so we
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* just have to punt.
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*/
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if ((start == 0) && (end == ~0)) {
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device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n",
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*rid, device_get_name(child), device_get_unit(child));
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} else {
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/*
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* Fail the allocation for this range if it's not supported.
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*
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* XXX we should probably just fix up the bridge decode and soldier on.
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*/
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switch (type) {
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case SYS_RES_IOPORT:
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if (!pcib_is_isa_io(start) &&
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((start < sc->iobase) || (end > sc->iolimit))) {
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device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx"
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" (decoding 0x%x-0x%x)\n",
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device_get_name(child), device_get_unit(child), start, end,
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sc->iobase, sc->iolimit);
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return (NULL);
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}
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if (bootverbose)
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device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n",
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device_get_name(child), device_get_unit(child), start, end);
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break;
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/*
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* XXX will have to decide whether the device making the request is asking
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* for prefetchable memory or not. If it's coming from another bridge
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* down the line, do we assume not, or ask the bridge to pass in another
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* flag as the request bubbles up?
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*/
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case SYS_RES_MEMORY:
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if (!pcib_is_isa_mem(start) &&
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(((start < sc->membase) || (end > sc->memlimit)) &&
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((start < sc->pmembase) || (end > sc->pmemlimit)))) {
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device_printf(dev, "device %s%d requested unsupported memory range 0x%lx-0x%lx"
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" (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
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device_get_name(child), device_get_unit(child), start, end,
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sc->membase, sc->memlimit, sc->pmembase, sc->pmemlimit);
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#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
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return(NULL);
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#endif
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}
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if (bootverbose)
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device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n",
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device_get_name(child), device_get_unit(child), start, end);
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break;
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default:
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break;
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}
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}
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/*
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* Bridge is OK decoding this resource, so pass it up.
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*/
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return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
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}
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/*
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* PCIB interface.
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*/
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static int
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pcib_maxslots(device_t dev)
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{
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return(PCI_SLOTMAX);
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}
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/*
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* Since we are a child of a PCI bus, its parent must support the pcib interface.
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*/
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static u_int32_t
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pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
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{
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return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
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}
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static void
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pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
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{
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PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
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}
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/*
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* Route an interrupt across a PCI bridge.
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*/
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static int
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pcib_route_interrupt(device_t pcib, device_t dev, int pin)
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{
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device_t bus;
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int parent_intpin;
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int intnum;
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/*
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*
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* The PCI standard defines a swizzle of the child-side device/intpin to
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* the parent-side intpin as follows.
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*
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* device = device on child bus
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* child_intpin = intpin on child bus slot (0-3)
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* parent_intpin = intpin on parent bus slot (0-3)
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*
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* parent_intpin = (device + child_intpin) % 4
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*/
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parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
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/*
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* Our parent is a PCI bus. Its parent must export the pcib interface
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* which includes the ability to route interrupts.
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*/
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bus = device_get_parent(pcib);
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intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
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device_printf(pcib, "routed slot %d INT%c to irq %d\n", pci_get_slot(dev),
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'A' + pin - 1, intnum);
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return(intnum);
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}
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