7453645f2a
All devices: - add support for rate adaptation via ieee80211_amrr(9); - use short preamble for transmitted frames when needed; - multi-bss support: * for RTL8821AU: 2 VAPs at the same time; * other: 1 any VAP + 1 sta VAP. RTL8188CE: - fix IQ calibration bug (reason of significant speed degradation); - add h/w crypto acceleration support. USB: - A-MPDU Tx support; - short GI support; Other: - add support for RTL8812AU / RTL8821AU chipsets (a/b/g/n only; no ac yet); - split merged code into subparts: * bus glue (usb/*, pci/*, rtl*/usb/*, rtl*/pci/*) * common (if_rtwn*) * chip-specific (rtl*/*) - various other bugfixes. Due to code reorganization, module names / requirements were changed too: urtwn urtwnfw -> rtwn rtwn_usb rtwnfw rtwn rtwnfw -> rtwn rtwn_pci rtwnfw Tested with RTL8188CE, RTL8188CUS, RTL8188EU and RTL8821AU. Tested by: kevlo, garga, Peter Garshtja <peter.garshtja@ambient-md.com>, Kevin McAleavey <kevin.mcaleavey@knosproject.com>, Ilias-Dimitrios Vrachnis <id@vrachnis.com>, <otacilio.neto@bsd.com.br> Relnotes: yes
104 lines
4.1 KiB
C
104 lines
4.1 KiB
C
/* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */
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/*-
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* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
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* Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef R92CE_REG_H
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#define R92CE_REG_H
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#include <dev/rtwn/rtl8192c/r92c_reg.h>
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/*
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* MAC registers.
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*/
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/* System Configuration. */
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#define R92C_PCIE_MIO_INTF 0x0e4
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#define R92C_PCIE_MIO_INTD 0x0e8
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/* PCIe Configuration. */
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#define R92C_PCIE_CTRL_REG 0x300
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#define R92C_INT_MIG 0x304
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#define R92C_BCNQ_DESA 0x308
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#define R92C_HQ_DESA 0x310
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#define R92C_MGQ_DESA 0x318
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#define R92C_VOQ_DESA 0x320
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#define R92C_VIQ_DESA 0x328
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#define R92C_BEQ_DESA 0x330
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#define R92C_BKQ_DESA 0x338
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#define R92C_RX_DESA 0x340
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#define R92C_DBI 0x348
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#define R92C_MDIO 0x354
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#define R92C_DBG_SEL 0x360
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#define R92C_PCIE_HRPWM 0x361
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#define R92C_PCIE_HCPWM 0x363
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#define R92C_UART_CTRL 0x364
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#define R92C_UART_TX_DES 0x370
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#define R92C_UART_RX_DES 0x378
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/* Bits for R92C_GPIO_MUXCFG. */
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#define R92C_GPIO_MUXCFG_RFKILL 0x0008
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/* Bits for R92C_GPIO_IO_SEL. */
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#define R92C_GPIO_IO_SEL_RFKILL 0x0008
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/* Bits for R92C_LEDCFG2. */
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#define R92C_LEDCFG2_EN 0x60
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#define R92C_LEDCFG2_DIS 0x68
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/* Bits for R92C_HIMR. */
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#define R92C_IMR_ROK 0x00000001 /* receive DMA OK */
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#define R92C_IMR_VODOK 0x00000002 /* AC_VO DMA OK */
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#define R92C_IMR_VIDOK 0x00000004 /* AC_VI DMA OK */
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#define R92C_IMR_BEDOK 0x00000008 /* AC_BE DMA OK */
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#define R92C_IMR_BKDOK 0x00000010 /* AC_BK DMA OK */
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#define R92C_IMR_TXBDER 0x00000020 /* beacon transmit error */
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#define R92C_IMR_MGNTDOK 0x00000040 /* management queue DMA OK */
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#define R92C_IMR_TBDOK 0x00000080 /* beacon transmit OK */
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#define R92C_IMR_HIGHDOK 0x00000100 /* high queue DMA OK */
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#define R92C_IMR_BDOK 0x00000200 /* beacon queue DMA OK */
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#define R92C_IMR_ATIMEND 0x00000400 /* ATIM window end interrupt */
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#define R92C_IMR_RDU 0x00000800 /* Rx descriptor unavailable */
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#define R92C_IMR_RXFOVW 0x00001000 /* receive FIFO overflow */
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#define R92C_IMR_BCNINT 0x00002000 /* beacon DMA interrupt 0 */
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#define R92C_IMR_PSTIMEOUT 0x00004000 /* powersave timeout */
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#define R92C_IMR_TXFOVW 0x00008000 /* transmit FIFO overflow */
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#define R92C_IMR_TIMEOUT1 0x00010000 /* timeout interrupt 1 */
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#define R92C_IMR_TIMEOUT2 0x00020000 /* timeout interrupt 2 */
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#define R92C_IMR_BCNDOK1 0x00040000 /* beacon queue DMA OK (1) */
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#define R92C_IMR_BCNDOK2 0x00080000 /* beacon queue DMA OK (2) */
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#define R92C_IMR_BCNDOK3 0x00100000 /* beacon queue DMA OK (3) */
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#define R92C_IMR_BCNDOK4 0x00200000 /* beacon queue DMA OK (4) */
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#define R92C_IMR_BCNDOK5 0x00400000 /* beacon queue DMA OK (5) */
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#define R92C_IMR_BCNDOK6 0x00800000 /* beacon queue DMA OK (6) */
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#define R92C_IMR_BCNDOK7 0x01000000 /* beacon queue DMA OK (7) */
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#define R92C_IMR_BCNDOK8 0x02000000 /* beacon queue DMA OK (8) */
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#define R92C_IMR_BCNDMAINT1 0x04000000 /* beacon DMA interrupt 1 */
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#define R92C_IMR_BCNDMAINT2 0x08000000 /* beacon DMA interrupt 2 */
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#define R92C_IMR_BCNDMAINT3 0x10000000 /* beacon DMA interrupt 3 */
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#define R92C_IMR_BCNDMAINT4 0x20000000 /* beacon DMA interrupt 4 */
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#define R92C_IMR_BCNDMAINT5 0x40000000 /* beacon DMA interrupt 5 */
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#define R92C_IMR_BCNDMAINT6 0x80000000 /* beacon DMA interrupt 6 */
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/* Shortcut. */
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#define R92C_IBSS_INT_MASK \
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(R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER)
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#endif /* R92CE_REG_H */
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