595 lines
22 KiB
C
595 lines
22 KiB
C
/*------------------------------------------------------------------
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* octeon_rgmx.h RGMII Ethernet Interfaces
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*
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*------------------------------------------------------------------
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*/
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#ifndef ___OCTEON_RGMX__H___
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#define ___OCTEON_RGMX__H___
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#define OCTEON_FPA_PACKET_POOL 0
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#define OCTEON_FPA_WQE_RX_POOL 1
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#define OCTEON_FPA_OUTPUT_BUFFER_POOL 2
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#define OCTEON_FPA_WQE_POOL_SIZE (1 * OCTEON_CACHE_LINE_SIZE)
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#define OCTEON_FPA_OUTPUT_BUFFER_POOL_SIZE (8 * OCTEON_CACHE_LINE_SIZE)
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#define OCTEON_FPA_PACKET_POOL_SIZE (16 * OCTEON_CACHE_LINE_SIZE)
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#define OCTEON_POW_WORK_REQUEST(wait) (0x8001600000000000ull | (wait<<3))
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typedef union
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{
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void* ptr;
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uint64_t word64;
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struct
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{
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uint64_t i : 1;
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uint64_t back : 4;
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uint64_t pool : 3;
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uint64_t size :16;
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uint64_t addr :40;
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} bits;
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} octeon_buf_ptr_t;
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/**
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* Work queue entry format
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*/
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typedef struct
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{
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uint16_t hw_chksum;
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uint8_t unused;
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uint64_t next_ptr : 40;
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uint64_t len :16;
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uint64_t ipprt : 6;
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uint64_t qos : 3;
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uint64_t grp : 4;
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uint64_t tag_type : 3;
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uint64_t tag :32;
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union
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{
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uint64_t word64;
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struct
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{
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uint64_t bufs : 8;
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uint64_t ip_offset : 8;
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uint64_t vlan_valid : 1;
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uint64_t unassigned : 2;
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uint64_t vlan_cfi : 1;
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uint64_t vlan_id :12;
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uint64_t unassigned2 :12;
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uint64_t dec_ipcomp : 1;
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uint64_t tcp_or_udp : 1;
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uint64_t dec_ipsec : 1;
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uint64_t is_v6 : 1;
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uint64_t software : 1;
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uint64_t L4_error : 1;
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uint64_t is_frag : 1;
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uint64_t IP_exc : 1;
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uint64_t is_bcast : 1;
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uint64_t is_mcast : 1;
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uint64_t not_IP : 1;
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uint64_t rcv_error : 1;
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uint64_t err_code : 8;
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} bits;
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struct
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{
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uint64_t bufs : 8;
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uint64_t unused : 8;
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uint64_t vlan_valid : 1;
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uint64_t unassigned : 2;
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uint64_t vlan_cfi : 1;
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uint64_t vlan_id :12;
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uint64_t unassigned2 :16;
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uint64_t software : 1;
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uint64_t unassigned3 : 1;
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uint64_t is_rarp : 1;
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uint64_t is_arp : 1;
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uint64_t is_bcast : 1;
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uint64_t is_mcast : 1;
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uint64_t not_IP : 1;
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uint64_t rcv_error : 1;
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uint64_t err_code : 8;
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} snoip;
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} word2;
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octeon_buf_ptr_t packet_ptr;
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uint8_t packet_data[96];
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} octeon_wqe_t;
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typedef union {
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uint64_t word64;
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struct {
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uint64_t scraddr : 8; /**< the (64-bit word) location in scratchpad to write to (if len != 0) */
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uint64_t len : 8; /**< the number of words in the response (0 => no response) */
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uint64_t did : 8; /**< the ID of the device on the non-coherent bus */
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uint64_t unused :36;
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uint64_t wait : 1; /**< if set, don't return load response until work is available */
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uint64_t unused2 : 3;
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} bits;
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} octeon_pow_iobdma_store_t;
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/**
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* Wait flag values for pow functions.
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*/
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typedef enum
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{
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OCTEON_POW_WAIT = 1,
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OCTEON_POW_NO_WAIT = 0,
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} octeon_pow_wait_t;
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static inline void * phys_to_virt (unsigned long address)
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{
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return (void *)(address + 0x80000000UL);
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}
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// decode within DMA space
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typedef enum {
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OCTEON_ADD_WIN_DMA_ADD = 0L, // add store data to the write buffer entry, allocating it if necessary
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OCTEON_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM
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// store data must be normal DRAM memory space address in this case
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OCTEON_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command
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// see OCTEON_ADD_WIN_DMA_SEND_DEC for data contents
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OCTEON_ADD_WIN_DMA_SENDIO = 3L, // send out the write buffer entry as an IO write
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// store data must be normal IO space address in this case
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OCTEON_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus
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// no write buffer data needed/used
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} octeon_add_win_dma_dec_t;
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#define OCTEON_OCT_DID_FPA 5ULL
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#define OCTEON_OCT_DID_TAG 12ULL
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#define OCTEON_OCT_DID_TAG_SWTAG OCTEON_ADDR_FULL_DID(OCTEON_OCT_DID_TAG, 0ULL)
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#define OCTEON_IOBDMA_OFFSET (-3*1024ll)
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#define OCTEON_IOBDMA_SEP 16
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#define OCTEON_IOBDMA_SENDSINGLE (OCTEON_IOBDMA_OFFSET + \
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(OCTEON_ADD_WIN_DMA_SENDSINGLE *\
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OCTEON_IOBDMA_SEP))
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static inline void octeon_send_single (uint64_t data)
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{
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oct_write64((uint64_t)(OCTEON_IOBDMA_SENDSINGLE * (long long)8), data);
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}
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static inline void octeon_pow_work_request_async_nocheck (int scratch_addr,
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octeon_pow_wait_t wait)
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{
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octeon_pow_iobdma_store_t data;
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/* scratch_addr must be 8 byte aligned */
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data.bits.scraddr = scratch_addr >> 3;
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data.bits.len = 1;
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data.bits.did = OCTEON_OCT_DID_TAG_SWTAG;
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data.bits.wait = wait;
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octeon_send_single(data.word64);
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}
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/**
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* octeon_gmx_inf_mode
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*
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* GMX_INF_MODE = Interface Mode
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*
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*/
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typedef union
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{
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uint64_t word64;
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struct gmxx_inf_mode_s
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{
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uint64_t reserved_3_63 : 61;
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uint64_t p0mii : 1; /**< Port 0 Interface Mode
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0: Port 0 is RGMII
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1: Port 0 is MII */
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uint64_t en : 1; /**< Interface Enable */
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uint64_t type : 1; /**< Interface Mode
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0: RGMII Mode
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1: Spi4 Mode */
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} bits;
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struct gmxx_inf_mode_cn3020
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{
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uint64_t reserved_2_63 : 62;
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uint64_t en : 1; /**< Interface Enable */
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uint64_t type : 1; /**< Interface Mode
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0: All three ports are RGMII ports
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1: prt0 is RGMII, prt1 is GMII, and prt2 is unused */
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} cn3020;
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struct gmxx_inf_mode_s cn30xx;
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struct gmxx_inf_mode_cn3020 cn31xx;
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struct gmxx_inf_mode_cn3020 cn36xx;
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struct gmxx_inf_mode_cn3020 cn38xx;
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struct gmxx_inf_mode_cn3020 cn38xxp2;
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struct gmxx_inf_mode_cn3020 cn56xx;
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struct gmxx_inf_mode_cn3020 cn58xx;
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} octeon_gmxx_inf_mode_t;
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 60; /* Reserved */
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uint64_t slottime : 1; /* Slot Time for Half-Duplex */
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/* operation - 0 = 512 bitimes (10/100Mbs operation) */
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/* - 1 = 4096 bitimes (1000Mbs operation) */
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uint64_t duplex : 1; /* Duplex - 0 = Half Duplex */
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/* (collisions/extentions/bursts) - 1 = Full Duplex */
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uint64_t speed : 1; /* Link Speed - 0 = 10/100Mbs */
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/* operation - 1 = 1000Mbs operation */
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uint64_t en : 1; /* Link Enable */
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} bits;
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} octeon_rgmx_prtx_cfg_t;
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/*
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* GMX_RX_INBND = RGMX InBand Link Status
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*
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*/
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typedef union {
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uint64_t word64;
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struct {
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uint64_t reserved : 60; /* Reserved */
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uint64_t duplex : 1; /* 0 = Half, 1 = Full */
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uint64_t speed : 2; /* Inbound Link Speed */
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/* 00 = 2.5Mhz, 01 = 25Mhz */
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/* 10 = 125MHz, 11 = Reserved */
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uint64_t status : 1; /* Inbound Status Up/Down */
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} bits;
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} octeon_rgmx_rxx_rx_inbnd_t;
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typedef union
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{
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uint64_t word64;
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struct {
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uint64_t all_drop : 32;
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uint64_t slow_drop : 32;
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} bits;
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} octeon_rgmx_ipd_queue_red_marks_t;
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typedef union
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{
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uint64_t word64;
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struct {
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uint64_t reserved : 15;
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uint64_t use_pagecount : 1;
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uint64_t new_con : 8;
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uint64_t avg_con : 8;
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uint64_t prb_con : 32;
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} bits;
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} octeon_rgmx_ipd_red_q_param_t;
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typedef union
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{
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uint64_t word64;
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struct {
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uint64_t reserved : 46;
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uint64_t bp_enable : 1;
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uint64_t page_count : 17;
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} bits;
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} octeon_ipd_port_bp_page_count_t;
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typedef union
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{
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uint64_t word64;
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struct {
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uint64_t prb_dly : 14;
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uint64_t avg_dly : 14;
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uint64_t port_enable : 36;
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} bits;
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} octeon_ipd_red_port_enable_t;
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/**
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* Tag type definitions
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*/
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typedef enum
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{
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OCTEON_POW_TAG_TYPE_ORDERED = 0L, /**< Tag ordering is maintained */
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OCTEON_POW_TAG_TYPE_ATOMIC = 1L, /**< Tag ordering is maintained, and at most one PP has the tag */
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OCTEON_POW_TAG_TYPE_NULL = 2L, /**< The work queue entry from the order
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- NEVER tag switch from NULL to NULL */
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OCTEON_POW_TAG_TYPE_NULL_NULL = 3L /**< A tag switch to NULL, and there is no space reserved in POW
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- NEVER tag switch to NULL_NULL
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- NEVER tag switch from NULL_NULL
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- NULL_NULL is entered at the beginning of time and on a deschedule.
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- NULL_NULL can be exited by a new work request. A NULL_SWITCH load can also switch the state to NULL */
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} octeon_pow_tag_type_t ;
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/**
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* This structure defines the response to a load/SENDSINGLE to POW (except CSR reads)
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*/
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typedef union {
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uint64_t word64;
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octeon_wqe_t *wqp;
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// response to new work request loads
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struct {
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uint64_t no_work : 1; // set when no new work queue entry was returned
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// If there was de-scheduled work, the HW will definitely
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// return it. When this bit is set, it could mean
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// either mean:
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// - There was no work, or
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// - There was no work that the HW could find. This
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// case can happen, regardless of the wait bit value
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// in the original request, when there is work
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// in the IQ's that is too deep down the list.
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uint64_t unused : 23;
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uint64_t addr : 40; // 36 in O1 -- the work queue pointer
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} s_work;
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// response to NULL_RD request loads
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struct {
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uint64_t unused : 62;
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uint64_t state : 2; // of type octeon_pow_tag_type_t
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// state is one of the following:
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// OCTEON_POW_TAG_TYPE_ORDERED
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// OCTEON_POW_TAG_TYPE_ATOMIC
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// OCTEON_POW_TAG_TYPE_NULL
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// OCTEON_POW_TAG_TYPE_NULL_NULL
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} s_null_rd;
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} octeon_pow_tag_load_resp_t;
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/*
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* This structure describes the address to load stuff from POW
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*/
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typedef union {
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uint64_t word64;
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// address for new work request loads (did<2:0> == 0)
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struct {
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uint64_t mem_region :2;
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uint64_t mbz :13;
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uint64_t is_io : 1; // must be one
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uint64_t did : 8; // the ID of POW -- did<2:0> == 0 in this case
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uint64_t unaddr : 4;
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uint64_t unused :32;
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uint64_t wait : 1; // if set, don't return load response until work is available
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uint64_t mbzl : 3; // must be zero
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} swork; // physical address
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// address for NULL_RD request (did<2:0> == 4)
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// when this is read, HW attempts to change the state to NULL if it is NULL_NULL
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// (the hardware cannot switch from NULL_NULL to NULL if a POW entry is not available -
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// software may need to recover by finishing another piece of work before a POW
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// entry can ever become available.)
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struct {
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uint64_t mem_region :2;
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uint64_t mbz :13;
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uint64_t is_io : 1; // must be one
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uint64_t did : 8; // the ID of POW -- did<2:0> == 4 in this case
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uint64_t unaddr : 4;
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uint64_t unused :33;
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uint64_t mbzl : 3; // must be zero
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} snull_rd; // physical address
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// address for CSR accesses
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struct {
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uint64_t mem_region :2;
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uint64_t mbz :13;
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uint64_t is_io : 1; // must be one
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uint64_t did : 8; // the ID of POW -- did<2:0> == 7 in this case
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uint64_t unaddr : 4;
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uint64_t csraddr:36; // only 36 bits in O1, addr<2:0> must be zero
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} stagcsr; // physical address
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} octeon_pow_load_addr_t;
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static inline void octeon_pow_tag_switch_wait (void)
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{
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uint64_t switch_complete;
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do
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{
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OCTEON_CHORD_HEX(&switch_complete);
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} while (!switch_complete);
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return;
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}
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static inline octeon_wqe_t *octeon_pow_work_request_sync_nocheck (octeon_pow_wait_t wait)
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{
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octeon_pow_load_addr_t ptr;
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octeon_pow_tag_load_resp_t result;
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ptr.word64 = 0;
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ptr.swork.mem_region = OCTEON_IO_SEG;
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ptr.swork.is_io = 1;
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ptr.swork.did = OCTEON_OCT_DID_TAG_SWTAG;
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ptr.swork.wait = wait;
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result.word64 = oct_read64(ptr.word64);
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if (result.s_work.no_work || !result.s_work.addr) {
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return NULL;
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}
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return (octeon_wqe_t *) OCTEON_PHYS2PTR(result.s_work.addr);
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}
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static inline octeon_wqe_t *octeon_pow_work_request_sync_nocheck_debug (octeon_pow_wait_t wait)
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{
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octeon_pow_load_addr_t ptr;
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octeon_pow_tag_load_resp_t result;
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ptr.word64 = 0;
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ptr.swork.mem_region = OCTEON_IO_SEG;
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ptr.swork.is_io = 1;
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ptr.swork.did = OCTEON_OCT_DID_TAG_SWTAG;
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ptr.swork.wait = wait;
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result.word64 = oct_read64(ptr.word64);
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printf("WQE Result: 0x%llX No-work %llX Addr %llX Ptr: %llX\n",
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result.word64, result.s_work.no_work, result.s_work.addr, OCTEON_PHYS2PTR(result.s_work.addr));
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if (result.s_work.no_work || !result.s_work.addr) {
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return NULL;
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}
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return (octeon_wqe_t *) OCTEON_PHYS2PTR(result.s_work.addr);
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}
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static inline octeon_wqe_t *octeon_pow_work_request_sync (octeon_pow_wait_t wait)
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{
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octeon_pow_tag_switch_wait();
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return (octeon_pow_work_request_sync_nocheck(wait));
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}
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static inline octeon_wqe_t *octeon_pow_work_request_sync_debug (octeon_pow_wait_t wait)
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{
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octeon_pow_tag_switch_wait();
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return (octeon_pow_work_request_sync_nocheck_debug(wait));
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}
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/**
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* Gets result of asynchronous work request. Performs a IOBDMA sync
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* to wait for the response.
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*
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* @param scratch_addr Scratch memory address to get result from
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* Byte address, must be 8 byte aligned.
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* @return Returns the WQE from the scratch register, or NULL if no work was available.
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*/
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static inline octeon_wqe_t *octeon_pow_work_response_async(int scratch_addr)
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{
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octeon_pow_tag_load_resp_t result;
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OCTEON_SYNCIOBDMA;
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result.word64 = oct_scratch_read64(scratch_addr);
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if (result.s_work.no_work) {
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return NULL;
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}
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return (octeon_wqe_t*) OCTEON_PHYS2PTR(result.s_work.addr);
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}
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/*
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* The address from POW is a physical address. Adjust for back ptr, as well as
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* make it accessible using KSEG0.
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*/
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static inline void *octeon_pow_pktptr_to_kbuffer (octeon_buf_ptr_t pkt_ptr)
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{
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return (OCTEON_PHYS2PTR(((pkt_ptr.bits.addr >> 7) - pkt_ptr.bits.back) << 7));
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}
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#define INTERFACE(port) (port >> 4) /* Ports 0-15 are interface 0, 16-31 are interface 1 */
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#define INDEX(port) (port & 0xf)
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#define OCTEON_RGMX_PRTX_CFG(index,interface) (0x8001180008000010ull+((index)*2048)+((interface)*0x8000000ull))
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#define OCTEON_RGMX_SMACX(offset,block_id) (0x8001180008000230ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM0(offset,block_id) (0x8001180008000180ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM1(offset,block_id) (0x8001180008000188ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM2(offset,block_id) (0x8001180008000190ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM3(offset,block_id) (0x8001180008000198ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM4(offset,block_id) (0x80011800080001A0ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM5(offset,block_id) (0x80011800080001A8ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CTL(offset,block_id) (0x8001180008000100ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_ADR_CAM_EN(offset,block_id) (0x8001180008000108ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_INF_MODE(block_id) (0x80011800080007F8ull+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_TX_PRTS(block_id) (0x8001180008000480ull+((block_id)*0x8000000ull))
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#define OCTEON_ASXX_RX_PRT_EN(block_id) (0x80011800B0000000ull+((block_id)*0x8000000ull))
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#define OCTEON_ASXX_TX_PRT_EN(block_id) (0x80011800B0000008ull+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_TXX_THRESH(offset,block_id) (0x8001180008000210ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_ASXX_TX_HI_WATERX(offset,block_id) (0x80011800B0000080ull+((offset)*8)+((block_id)*0x8000000ull))
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#define OCTEON_ASXX_RX_CLK_SETX(offset,block_id) (0x80011800B0000020ull+((offset)*8)+((block_id)*0x8000000ull))
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#define OCTEON_ASXX_TX_CLK_SETX(offset,block_id) (0x80011800B0000048ull+((offset)*8)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_RXX_RX_INBND(offset,block_id) (0x8001180008000060ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_TXX_CLK(offset,block_id) (0x8001180008000208ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_TXX_SLOT(offset,block_id) (0x8001180008000220ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_RGMX_TXX_BURST(offset,block_id) (0x8001180008000228ull+((offset)*2048)+((block_id)*0x8000000ull))
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#define OCTEON_PIP_GBL_CTL (0x80011800A0000020ull)
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#define OCTEON_PIP_GBL_CFG (0x80011800A0000028ull)
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#define OCTEON_PIP_PRT_CFGX(offset) (0x80011800A0000200ull+((offset)*8))
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#define OCTEON_PIP_PRT_TAGX(offset) (0x80011800A0000400ull+((offset)*8))
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#define OUR_CORE 0
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#define IP2 0
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#define IP3 1
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#define CIU_TIMERS 4
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#define OCTEON_POW_CORE_GROUP_MASK(core) (0x8001670000000000ull + (8 * core))
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#define OCTEON_CIU_INT_EN0(CORE,IP) (0x8001070000000200ull + (IP * 16) + \
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((CORE) * 32))
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#define OCTEON_CIU_INT_SUM0(CORE,IP) (0x8001070000000000ull + (IP * 8) + \
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((CORE) * 32))
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#define OCTEON_CIU_TIMX(offset) (0x8001070000000480ull+((offset)*8))
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#define OCTEON_POW_WQ_INT_THRX(offset) ((0x8001670000000080ull+((offset)*8)))
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#define OCTEON_POW_WQ_INT_CNTX(offset) ((0x8001670000000100ull+((offset)*8)))
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#define OCTEON_POW_QOS_THRX(offset) ((0x8001670000000180ull+((offset)*8)))
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#define OCTEON_POW_QOS_RNDX(offset) ((0x80016700000001C0ull+((offset)*8)))
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#define OCTEON_POW_WQ_INT_PC (0x8001670000000208ull)
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#define OCTEON_POW_NW_TIM (0x8001670000000210ull)
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#define OCTEON_POW_ECC_ERR (0x8001670000000218ull)
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#define OCTEON_POW_INT_CTL (0x8001670000000220ull)
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#define OCTEON_POW_NOS_CNT (0x8001670000000228ull)
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#define OCTEON_POW_WS_PCX(offset) ((0x8001670000000280ull+((offset)*8)))
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#define OCTEON_POW_WA_PCX(offset) ((0x8001670000000300ull+((offset)*8)))
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#define OCTEON_POW_IQ_CNTX(offset) ((0x8001670000000340ull+((offset)*8)))
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#define OCTEON_POW_WA_COM_PC (0x8001670000000380ull)
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#define OCTEON_POW_IQ_COM_CNT (0x8001670000000388ull)
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#define OCTEON_POW_TS_PC (0x8001670000000390ull)
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#define OCTEON_POW_DS_PC (0x8001670000000398ull)
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#define OCTEON_POW_BIST_STAT (0x80016700000003F8ull)
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#define OCTEON_POW_WQ_INT (0x8001670000000200ull)
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#define OCTEON_IPD_PORT_BP_COUNTERS_PAIRX(offset) (0x80014F00000001B8ull+((offset)*8))
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/*
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* Current Counts that triggered interrupt
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*/
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#define OCTEON_POW_WQ_INT_CNTX(offset) ((0x8001670000000100ull+((offset)*8)))
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#define OCTEON_RGMX_ADRCTL_CAM_MODE_REJECT_DMAC 0
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#define OCTEON_RGMX_ADRCTL_ACCEPT_BROADCAST 1
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#define OCTEON_RGMX_ADRCTL_REJECT_ALL_MULTICAST 2
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#define OCTEON_RGMX_ADRCTL_ACCEPT_ALL_MULTICAST 4
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#define OCTEON_RGMX_ADRCTL_CAM_MODE_ACCEPT_DMAC 8
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#define RGMX_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
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#define RGMX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
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#define RGMX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define RGMX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define RGMX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
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#endif /* ___OCTEON_RGMX__H___ */
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