505 lines
17 KiB
C
505 lines
17 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2003 Peter Wemm.
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Derived from hp300 version by Mike Hibler, this version by William
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* Jolitz uses a recursive map [a pde points to the page directory] to
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* map the page tables using the pagetables themselves. This is done to
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* reduce the impact on kernel virtual memory for lots of sparse address
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* space, and to reduce the cost of memory to each process.
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*
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* from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
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* from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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/*
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* Page-directory and page-table entries follow this format, with a few
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* of the fields not present here and there, depending on a lot of things.
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*/
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/* ---- Intel Nomenclature ---- */
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#define X86_PG_V 0x001 /* P Valid */
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#define X86_PG_RW 0x002 /* R/W Read/Write */
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#define X86_PG_U 0x004 /* U/S User/Supervisor */
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#define X86_PG_NC_PWT 0x008 /* PWT Write through */
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#define X86_PG_NC_PCD 0x010 /* PCD Cache disable */
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#define X86_PG_A 0x020 /* A Accessed */
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#define X86_PG_M 0x040 /* D Dirty */
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#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
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#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */
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#define X86_PG_G 0x100 /* G Global */
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#define X86_PG_AVAIL1 0x200 /* / Available for system */
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#define X86_PG_AVAIL2 0x400 /* < programmers use */
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#define X86_PG_AVAIL3 0x800 /* \ */
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#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */
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#define X86_PG_PKU(idx) ((pt_entry_t)idx << 59)
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#define X86_PG_NX (1ul<<63) /* No-execute */
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#define X86_PG_AVAIL(x) (1ul << (x))
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/* Page level cache control fields used to determine the PAT type */
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#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
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#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
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/* Protection keys indexes */
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#define PMAP_MAX_PKRU_IDX 0xf
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#define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX)
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/*
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* Intel extended page table (EPT) bit definitions.
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*/
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#define EPT_PG_READ 0x001 /* R Read */
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#define EPT_PG_WRITE 0x002 /* W Write */
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#define EPT_PG_EXECUTE 0x004 /* X Execute */
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#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */
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#define EPT_PG_PS 0x080 /* PS Page size */
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#define EPT_PG_A 0x100 /* A Accessed */
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#define EPT_PG_M 0x200 /* D Dirty */
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#define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */
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/*
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* Define the PG_xx macros in terms of the bits on x86 PTEs.
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*/
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#define PG_V X86_PG_V
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#define PG_RW X86_PG_RW
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#define PG_U X86_PG_U
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#define PG_NC_PWT X86_PG_NC_PWT
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#define PG_NC_PCD X86_PG_NC_PCD
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#define PG_A X86_PG_A
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#define PG_M X86_PG_M
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#define PG_PS X86_PG_PS
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#define PG_PTE_PAT X86_PG_PTE_PAT
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#define PG_G X86_PG_G
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#define PG_AVAIL1 X86_PG_AVAIL1
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#define PG_AVAIL2 X86_PG_AVAIL2
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#define PG_AVAIL3 X86_PG_AVAIL3
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#define PG_PDE_PAT X86_PG_PDE_PAT
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#define PG_NX X86_PG_NX
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#define PG_PDE_CACHE X86_PG_PDE_CACHE
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#define PG_PTE_CACHE X86_PG_PTE_CACHE
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/* Our various interpretations of the above */
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#define PG_W X86_PG_AVAIL3 /* "Wired" pseudoflag */
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#define PG_MANAGED X86_PG_AVAIL2
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#define EPT_PG_EMUL_V X86_PG_AVAIL(52)
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#define EPT_PG_EMUL_RW X86_PG_AVAIL(53)
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#define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */
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#define PG_FRAME (0x000ffffffffff000ul)
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#define PG_PS_FRAME (0x000fffffffe00000ul)
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#define PG_PS_PDP_FRAME (0x000fffffc0000000ul)
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/*
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* Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
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* (PTE) page mappings have identical settings for the following fields:
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*/
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#define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \
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PG_M | PG_A | PG_U | PG_RW | PG_V | PG_PKU_MASK)
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/*
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* Page Protection Exception bits
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*/
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#define PGEX_P 0x01 /* Protection violation vs. not present */
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#define PGEX_W 0x02 /* during a Write cycle */
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#define PGEX_U 0x04 /* access from User mode (UPL) */
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#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
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#define PGEX_I 0x10 /* during an instruction fetch */
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#define PGEX_PK 0x20 /* protection key violation */
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#define PGEX_SGX 0x8000 /* SGX-related */
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/*
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* undef the PG_xx macros that define bits in the regular x86 PTEs that
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* have a different position in nested PTEs. This is done when compiling
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* code that needs to be aware of the differences between regular x86 and
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* nested PTEs.
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*
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* The appropriate bitmask will be calculated at runtime based on the pmap
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* type.
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*/
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#ifdef AMD64_NPT_AWARE
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#undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */
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#undef PG_G
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#undef PG_A
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#undef PG_M
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#undef PG_PDE_PAT
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#undef PG_PDE_CACHE
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#undef PG_PTE_PAT
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#undef PG_PTE_CACHE
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#undef PG_RW
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#undef PG_V
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#endif
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/*
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* Pte related macros. This is complicated by having to deal with
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* the sign extension of the 48th bit.
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*/
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#define KVADDR(l4, l3, l2, l1) ( \
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((unsigned long)-1 << 47) | \
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((unsigned long)(l4) << PML4SHIFT) | \
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((unsigned long)(l3) << PDPSHIFT) | \
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((unsigned long)(l2) << PDRSHIFT) | \
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((unsigned long)(l1) << PAGE_SHIFT))
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#define UVADDR(l4, l3, l2, l1) ( \
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((unsigned long)(l4) << PML4SHIFT) | \
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((unsigned long)(l3) << PDPSHIFT) | \
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((unsigned long)(l2) << PDRSHIFT) | \
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((unsigned long)(l1) << PAGE_SHIFT))
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/*
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* Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so,
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* but setting it larger than NDMPML4E makes no sense.
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*
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* Each slot provides .5 TB of kernel virtual space.
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*/
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#define NKPML4E 4
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#define NUPML4E (NPML4EPG/2) /* number of userland PML4 pages */
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#define NUPDPE (NUPML4E*NPDPEPG)/* number of userland PDP pages */
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#define NUPDE (NUPDPE*NPDEPG) /* number of userland PD entries */
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/*
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* NDMPML4E is the maximum number of PML4 entries that will be
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* used to implement the direct map. It must be a power of two,
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* and should generally exceed NKPML4E. The maximum possible
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* value is 64; using 128 will make the direct map intrude into
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* the recursive page table map.
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*/
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#define NDMPML4E 8
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/*
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* These values control the layout of virtual memory. The starting address
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* of the direct map, which is controlled by DMPML4I, must be a multiple of
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* its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.)
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*
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* Note: KPML4I is the index of the (single) level 4 page that maps
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* the KVA that holds KERNBASE, while KPML4BASE is the index of the
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* first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E
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* is 1, these are the same, otherwise KPML4BASE < KPML4I and extra
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* level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to
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* KERNBASE.
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*
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* (KPML4I combines with KPDPI to choose where KERNBASE starts.
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* Or, in other words, KPML4I provides bits 39..47 of KERNBASE,
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* and KPDPI provides bits 30..38.)
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*/
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#define PML4PML4I (NPML4EPG/2) /* Index of recursive pml4 mapping */
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#define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */
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#define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */
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#define KPML4I (NPML4EPG-1)
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#define KPDPI (NPDPEPG-2) /* kernbase at -2GB */
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/* Large map: index of the first and max last pml4 entry */
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#define LMSPML4I (PML4PML4I + 1)
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#define LMEPML4I (DMPML4I - 1)
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/*
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* XXX doesn't really belong here I guess...
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*/
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#define ISA_HOLE_START 0xa0000
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#define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START)
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#define PMAP_PCID_NONE 0xffffffff
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#define PMAP_PCID_KERN 0
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#define PMAP_PCID_OVERMAX 0x1000
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#define PMAP_PCID_OVERMAX_KERN 0x800
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#define PMAP_PCID_USER_PT 0x800
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#define PMAP_NO_CR3 (~0UL)
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#ifndef LOCORE
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#include <sys/queue.h>
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#include <sys/_cpuset.h>
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#include <sys/_lock.h>
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#include <sys/_mutex.h>
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#include <sys/_pctrie.h>
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#include <sys/_rangeset.h>
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#include <vm/_vm_radix.h>
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typedef u_int64_t pd_entry_t;
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typedef u_int64_t pt_entry_t;
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typedef u_int64_t pdp_entry_t;
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typedef u_int64_t pml4_entry_t;
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/*
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* Address of current address space page table maps and directories.
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*/
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#ifdef _KERNEL
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#define addr_PTmap (KVADDR(PML4PML4I, 0, 0, 0))
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#define addr_PDmap (KVADDR(PML4PML4I, PML4PML4I, 0, 0))
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#define addr_PDPmap (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0))
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#define addr_PML4map (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I))
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#define addr_PML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t)))
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#define PTmap ((pt_entry_t *)(addr_PTmap))
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#define PDmap ((pd_entry_t *)(addr_PDmap))
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#define PDPmap ((pd_entry_t *)(addr_PDPmap))
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#define PML4map ((pd_entry_t *)(addr_PML4map))
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#define PML4pml4e ((pd_entry_t *)(addr_PML4pml4e))
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extern int nkpt; /* Initial number of kernel page tables */
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extern u_int64_t KPDPphys; /* physical address of kernel level 3 */
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extern u_int64_t KPML4phys; /* physical address of kernel level 4 */
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/*
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* virtual address to page table entry and
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* to physical address.
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* Note: these work recursively, thus vtopte of a pte will give
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* the corresponding pde that in turn maps it.
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*/
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pt_entry_t *vtopte(vm_offset_t);
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#define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
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#define pte_load_store(ptep, pte) atomic_swap_long(ptep, pte)
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#define pte_load_clear(ptep) atomic_swap_long(ptep, 0)
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#define pte_store(ptep, pte) do { \
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*(u_long *)(ptep) = (u_long)(pte); \
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} while (0)
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#define pte_clear(ptep) pte_store(ptep, 0)
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#define pde_store(pdep, pde) pte_store(pdep, pde)
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extern pt_entry_t pg_nx;
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#endif /* _KERNEL */
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/*
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* Pmap stuff
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*/
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struct pv_entry;
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struct pv_chunk;
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/*
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* Locks
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* (p) PV list lock
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*/
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struct md_page {
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TAILQ_HEAD(, pv_entry) pv_list; /* (p) */
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int pv_gen; /* (p) */
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int pat_mode;
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};
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enum pmap_type {
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PT_X86, /* regular x86 page tables */
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PT_EPT, /* Intel's nested page tables */
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PT_RVI, /* AMD's nested page tables */
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};
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struct pmap_pcids {
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uint32_t pm_pcid;
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uint32_t pm_gen;
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};
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/*
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* The kernel virtual address (KVA) of the level 4 page table page is always
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* within the direct map (DMAP) region.
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*/
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struct pmap {
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struct mtx pm_mtx;
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pml4_entry_t *pm_pml4; /* KVA of level 4 page table */
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pml4_entry_t *pm_pml4u; /* KVA of user l4 page table */
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uint64_t pm_cr3;
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uint64_t pm_ucr3;
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TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
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cpuset_t pm_active; /* active on cpus */
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enum pmap_type pm_type; /* regular or nested tables */
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struct pmap_statistics pm_stats; /* pmap statistics */
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struct vm_radix pm_root; /* spare page table pages */
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long pm_eptgen; /* EPT pmap generation id */
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int pm_flags;
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struct pmap_pcids pm_pcids[MAXCPU];
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struct rangeset pm_pkru;
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};
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/* flags */
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#define PMAP_NESTED_IPIMASK 0xff
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#define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */
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#define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */
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#define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */
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typedef struct pmap *pmap_t;
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#ifdef _KERNEL
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extern struct pmap kernel_pmap_store;
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#define kernel_pmap (&kernel_pmap_store)
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#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
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#define PMAP_LOCK_ASSERT(pmap, type) \
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mtx_assert(&(pmap)->pm_mtx, (type))
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#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
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#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
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NULL, MTX_DEF | MTX_DUPOK)
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#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
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#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
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#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
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#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
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int pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags);
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int pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype);
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#endif
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/*
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* For each vm_page_t, there is a list of all currently valid virtual
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* mappings of that page. An entry is a pv_entry_t, the list is pv_list.
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*/
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typedef struct pv_entry {
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vm_offset_t pv_va; /* virtual address for mapping */
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TAILQ_ENTRY(pv_entry) pv_next;
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} *pv_entry_t;
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/*
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* pv_entries are allocated in chunks per-process. This avoids the
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* need to track per-pmap assignments.
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*/
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#define _NPCM 3
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#define _NPCPV 168
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#define PV_CHUNK_HEADER \
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pmap_t pc_pmap; \
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TAILQ_ENTRY(pv_chunk) pc_list; \
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uint64_t pc_map[_NPCM]; /* bitmap; 1 = free */ \
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TAILQ_ENTRY(pv_chunk) pc_lru;
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struct pv_chunk_header {
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PV_CHUNK_HEADER
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};
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struct pv_chunk {
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PV_CHUNK_HEADER
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struct pv_entry pc_pventry[_NPCPV];
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};
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#ifdef _KERNEL
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extern caddr_t CADDR1;
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extern pt_entry_t *CMAP1;
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extern vm_offset_t virtual_avail;
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extern vm_offset_t virtual_end;
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extern vm_paddr_t dmaplimit;
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extern int pmap_pcid_enabled;
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extern int invpcid_works;
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#define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode)
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#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
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#define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz))
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struct thread;
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void pmap_activate_boot(pmap_t pmap);
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void pmap_activate_sw(struct thread *);
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void pmap_bootstrap(vm_paddr_t *);
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int pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde);
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int pmap_change_attr(vm_offset_t, vm_size_t, int);
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void pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate);
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void pmap_flush_cache_range(vm_offset_t, vm_offset_t);
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void pmap_flush_cache_phys_range(vm_paddr_t, vm_paddr_t, vm_memattr_t);
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void pmap_init_pat(void);
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void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
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void *pmap_kenter_temporary(vm_paddr_t pa, int i);
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vm_paddr_t pmap_kextract(vm_offset_t);
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void pmap_kremove(vm_offset_t);
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int pmap_large_map(vm_paddr_t, vm_size_t, void **, vm_memattr_t);
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void pmap_large_map_wb(void *sva, vm_size_t len);
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void pmap_large_unmap(void *sva, vm_size_t len);
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void *pmap_mapbios(vm_paddr_t, vm_size_t);
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void *pmap_mapdev(vm_paddr_t, vm_size_t);
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void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int);
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void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size);
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bool pmap_not_in_di(void);
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boolean_t pmap_page_is_mapped(vm_page_t m);
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void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
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void pmap_pinit_pml4(vm_page_t);
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bool pmap_ps_enabled(pmap_t pmap);
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void pmap_unmapdev(vm_offset_t, vm_size_t);
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void pmap_invalidate_page(pmap_t, vm_offset_t);
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void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
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void pmap_invalidate_all(pmap_t);
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void pmap_invalidate_cache(void);
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void pmap_invalidate_cache_pages(vm_page_t *pages, int count);
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void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
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void pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva);
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void pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num);
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boolean_t pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
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void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
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void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec);
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void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva);
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void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3);
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void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va);
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void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva,
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vm_offset_t eva);
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int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
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int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
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u_int keyidx, int flags);
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void pmap_thread_init_invl_gen(struct thread *td);
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int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap);
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void pmap_page_array_startup(long count);
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#endif /* _KERNEL */
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/* Return various clipped indexes for a given VA */
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static __inline vm_pindex_t
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pmap_pte_index(vm_offset_t va)
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{
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return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
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}
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static __inline vm_pindex_t
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pmap_pde_index(vm_offset_t va)
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{
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return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
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}
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static __inline vm_pindex_t
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pmap_pdpe_index(vm_offset_t va)
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{
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return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
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}
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static __inline vm_pindex_t
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pmap_pml4e_index(vm_offset_t va)
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{
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return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
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}
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#endif /* !LOCORE */
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#endif /* !_MACHINE_PMAP_H_ */
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