130 lines
4.7 KiB
C++
130 lines
4.7 KiB
C++
//===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//===----------------------------------------------------------------------===//
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#include "LiveRangeEdit.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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LiveInterval &LiveRangeEdit::create(MachineRegisterInfo &mri,
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LiveIntervals &lis,
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VirtRegMap &vrm) {
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const TargetRegisterClass *RC = mri.getRegClass(getReg());
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unsigned VReg = mri.createVirtualRegister(RC);
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vrm.grow();
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vrm.setIsSplitFromReg(VReg, vrm.getOriginal(getReg()));
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LiveInterval &li = lis.getOrCreateInterval(VReg);
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newRegs_.push_back(&li);
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return li;
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}
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void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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for (LiveInterval::vni_iterator I = parent_.vni_begin(),
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E = parent_.vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->isUnused())
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continue;
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MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
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if (!DefMI)
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continue;
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if (tii.isTriviallyReMaterializable(DefMI, aa))
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remattable_.insert(VNI);
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}
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scannedRemattable_ = true;
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}
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bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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if (!scannedRemattable_)
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scanRemattable(lis, tii, aa);
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return !remattable_.empty();
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}
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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SlotIndex OrigIdx,
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SlotIndex UseIdx,
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LiveIntervals &lis) {
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OrigIdx = OrigIdx.getUseIndex();
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UseIdx = UseIdx.getUseIndex();
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for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = OrigMI->getOperand(i);
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if (!MO.isReg() || !MO.getReg() || MO.getReg() == getReg())
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continue;
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// Reserved registers are OK.
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if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
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continue;
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// We don't want to move any defs.
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if (MO.isDef())
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return false;
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// We cannot depend on virtual registers in uselessRegs_.
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for (unsigned ui = 0, ue = uselessRegs_.size(); ui != ue; ++ui)
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if (uselessRegs_[ui]->reg == MO.getReg())
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return false;
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LiveInterval &li = lis.getInterval(MO.getReg());
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const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
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if (!OVNI)
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continue;
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if (OVNI != li.getVNInfoAt(UseIdx))
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return false;
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}
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return true;
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}
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bool LiveRangeEdit::canRematerializeAt(Remat &RM,
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SlotIndex UseIdx,
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bool cheapAsAMove,
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LiveIntervals &lis) {
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assert(scannedRemattable_ && "Call anyRematerializable first");
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// Use scanRemattable info.
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if (!remattable_.count(RM.ParentVNI))
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return false;
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// No defining instruction.
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RM.OrigMI = lis.getInstructionFromIndex(RM.ParentVNI->def);
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assert(RM.OrigMI && "Defining instruction for remattable value disappeared");
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// If only cheap remats were requested, bail out early.
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if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
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return false;
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// Verify that all used registers are available with the same values.
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if (!allUsesAvailableAt(RM.OrigMI, RM.ParentVNI->def, UseIdx, lis))
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return false;
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return true;
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}
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SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const Remat &RM,
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LiveIntervals &lis,
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const TargetInstrInfo &tii,
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const TargetRegisterInfo &tri) {
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assert(RM.OrigMI && "Invalid remat");
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tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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rematted_.insert(RM.ParentVNI);
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return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
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}
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