d14b0ac129
includes support for the NIC and TOE features of the 40G, 10G, and 1G/100M cards based on the T5. The ASIC is mostly backward compatible with the Terminator 4 so cxgbe(4) has been updated instead of writing a brand new driver. T5 cards will show up as cxl (short for cxlgb) ports attached to the t5nex bus driver. Sponsored by: Chelsio
241 lines
8.0 KiB
C
241 lines
8.0 KiB
C
/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* All rights reserved.
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* Written by: Navdeep Parhar <np@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __T4_IOCTL_H__
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#define __T4_IOCTL_H__
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#include <sys/types.h>
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#include <net/ethernet.h>
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/*
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* Ioctl commands specific to this driver.
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*/
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enum {
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T4_GETREG = 0x40, /* read register */
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T4_SETREG, /* write register */
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T4_REGDUMP, /* dump of all registers */
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T4_GET_FILTER_MODE, /* get global filter mode */
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T4_SET_FILTER_MODE, /* set global filter mode */
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T4_GET_FILTER, /* get information about a filter */
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T4_SET_FILTER, /* program a filter */
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T4_DEL_FILTER, /* delete a filter */
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T4_GET_SGE_CONTEXT, /* get SGE context for a queue */
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T4_LOAD_FW, /* flash firmware */
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T4_GET_MEM, /* read memory */
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T4_GET_I2C, /* read from i2c addressible device */
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T4_CLEAR_STATS, /* clear a port's MAC statistics */
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};
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struct t4_reg {
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uint32_t addr;
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uint32_t size;
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uint64_t val;
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};
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#define T4_REGDUMP_SIZE (160 * 1024)
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#define T5_REGDUMP_SIZE (332 * 1024)
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struct t4_regdump {
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uint32_t version;
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uint32_t len; /* bytes */
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uint32_t *data;
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};
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struct t4_data {
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uint32_t len;
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uint8_t *data;
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};
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struct t4_i2c_data {
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uint8_t port_id;
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uint8_t dev_addr;
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uint8_t offset;
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uint8_t len;
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uint8_t data[8];
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};
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/*
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* A hardware filter is some valid combination of these.
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*/
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#define T4_FILTER_IPv4 0x1 /* IPv4 packet */
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#define T4_FILTER_IPv6 0x2 /* IPv6 packet */
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#define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */
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#define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */
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#define T4_FILTER_IP_SPORT 0x10 /* Source IP port */
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#define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */
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#define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */
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#define T4_FILTER_PORT 0x80 /* Physical ingress port */
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#define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */
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#define T4_FILTER_VLAN 0x200 /* VLAN ID */
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#define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */
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#define T4_FILTER_IP_PROTO 0x800 /* IP protocol */
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#define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */
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#define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */
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#define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */
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#define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */
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/* Filter action */
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enum {
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FILTER_PASS = 0, /* default */
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FILTER_DROP,
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FILTER_SWITCH
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};
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/* 802.1q manipulation on FILTER_SWITCH */
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enum {
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VLAN_NOCHANGE = 0, /* default */
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VLAN_REMOVE,
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VLAN_INSERT,
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VLAN_REWRITE
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};
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/* MPS match type */
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enum {
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UCAST_EXACT = 0, /* exact unicast match */
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UCAST_HASH = 1, /* inexact (hashed) unicast match */
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MCAST_EXACT = 2, /* exact multicast match */
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MCAST_HASH = 3, /* inexact (hashed) multicast match */
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PROMISC = 4, /* no match but port is promiscuous */
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HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */
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BCAST = 6, /* broadcast packet */
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};
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/* Rx steering */
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enum {
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DST_MODE_QUEUE, /* queue is directly specified by filter */
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DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */
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DST_MODE_RSS, /* queue selected by default RSS hash lookup */
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DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified
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RSS subtable */
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};
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struct t4_filter_tuple {
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/*
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* These are always available.
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*/
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uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */
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uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */
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uint16_t sport; /* source port */
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uint16_t dport; /* destination port */
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/*
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* A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP
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* is used to select the global mode and all filters are limited to the
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* set of fields allowed by the global mode.
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*/
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uint16_t vnic; /* VNIC id or outer VLAN tag */
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uint16_t vlan; /* VLAN tag */
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uint16_t ethtype; /* Ethernet type */
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uint8_t tos; /* TOS/Traffic Type */
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uint8_t proto; /* protocol type */
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uint32_t fcoe:1; /* FCoE packet */
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uint32_t iport:3; /* ingress port */
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uint32_t matchtype:3; /* MPS match type */
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uint32_t frag:1; /* fragmentation extension header */
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uint32_t macidx:9; /* exact match MAC index */
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uint32_t vlan_vld:1; /* VLAN valid */
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uint32_t vnic_vld:1; /* VNIC id/outer VLAN tag valid */
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};
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struct t4_filter_specification {
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uint32_t hitcnts:1; /* count filter hits in TCB */
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uint32_t prio:1; /* filter has priority over active/server */
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uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
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uint32_t action:2; /* drop, pass, switch */
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uint32_t rpttid:1; /* report TID in RSS hash field */
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uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
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uint32_t iq:10; /* ingress queue */
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uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
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uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
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/* 1 => TCB contains IQ ID */
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/*
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* Switch proxy/rewrite fields. An ingress packet which matches a
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* filter with "switch" set will be looped back out as an egress
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* packet -- potentially with some Ethernet header rewriting.
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*/
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uint32_t eport:2; /* egress port to switch packet out */
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uint32_t newdmac:1; /* rewrite destination MAC address */
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uint32_t newsmac:1; /* rewrite source MAC address */
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uint32_t newvlan:2; /* rewrite VLAN Tag */
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uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */
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uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */
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uint16_t vlan; /* VLAN Tag to insert */
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/*
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* Filter rule value/mask pairs.
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*/
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struct t4_filter_tuple val;
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struct t4_filter_tuple mask;
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};
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struct t4_filter {
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uint32_t idx;
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uint16_t l2tidx;
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uint16_t smtidx;
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uint64_t hits;
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struct t4_filter_specification fs;
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};
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#define T4_SGE_CONTEXT_SIZE 24
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enum {
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SGE_CONTEXT_EGRESS,
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SGE_CONTEXT_INGRESS,
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SGE_CONTEXT_FLM,
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SGE_CONTEXT_CNM
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};
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struct t4_sge_context {
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uint32_t mem_id;
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uint32_t cid;
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uint32_t data[T4_SGE_CONTEXT_SIZE / 4];
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};
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struct t4_mem_range {
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uint32_t addr;
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uint32_t len;
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uint32_t *data;
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};
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#define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg)
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#define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg)
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#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump)
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#define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t)
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#define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t)
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#define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter)
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#define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter)
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#define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter)
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#define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \
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struct t4_sge_context)
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#define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data)
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#define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range)
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#define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data)
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#define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t)
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#endif
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