d1d3233ebd
The following systems are affected:
- MPC8555CDS
- MPC8572DS
This overhaul covers the following major changes:
- All integrated peripherals drivers for Freescale MPC85XX SoC, which are
currently in the FreeBSD source tree are reworked and adjusted so they
derive config data out of the device tree blob (instead of hard coded /
tabelarized values).
- This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC,
QUICC, UART, CFI.
- Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire
ocpbus(4) driver, which was based on hard-coded config data.
Note that world for these platforms has to be built WITH_FDT.
Reviewed by: imp
Sponsored by: The FreeBSD Foundation
192 lines
4.3 KiB
C
192 lines
4.3 KiB
C
/*-
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* Copyright (C) 2008 Semihalf, Rafal Jaworowski
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/spr.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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/*
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* MPC85xx system specific routines
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*/
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uint32_t
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ccsr_read4(uintptr_t addr)
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{
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volatile uint32_t *ptr = (void *)addr;
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return (*ptr);
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}
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void
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ccsr_write4(uintptr_t addr, uint32_t val)
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{
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volatile uint32_t *ptr = (void *)addr;
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*ptr = val;
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__asm __volatile("eieio; sync");
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}
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int
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law_getmax(void)
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{
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uint32_t ver;
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
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return (12);
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else if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
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return (10);
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else
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return (8);
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}
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#define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
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#define _LAW_BAR(addr) (addr >> 12)
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int
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law_enable(int trgt, u_long addr, u_long size)
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{
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uint32_t bar, sr;
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int i, law_max;
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law_max = law_getmax();
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bar = _LAW_BAR(addr);
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sr = _LAW_SR(trgt, size);
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/* Bail if already programmed. */
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for (i = 0; i < law_max; i++)
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if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
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bar == ccsr_read4(OCP85XX_LAWBAR(i)))
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return (0);
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/* Find an unused access window. */
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for (i = 0; i < law_max; i++)
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if ((ccsr_read4(OCP85XX_LAWSR(i)) & 0x80000000) == 0)
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break;
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if (i == law_max)
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return (ENOSPC);
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ccsr_write4(OCP85XX_LAWBAR(i), bar);
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ccsr_write4(OCP85XX_LAWSR(i), sr);
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return (0);
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}
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int
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law_disable(int trgt, u_long addr, u_long size)
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{
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uint32_t bar, sr;
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int i, law_max;
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law_max = law_getmax();
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bar = _LAW_BAR(addr);
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sr = _LAW_SR(trgt, size);
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/* Find and disable requested LAW. */
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for (i = 0; i < law_max; i++)
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if (sr == ccsr_read4(OCP85XX_LAWSR(i)) &&
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bar == ccsr_read4(OCP85XX_LAWBAR(i))) {
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ccsr_write4(OCP85XX_LAWBAR(i), 0);
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ccsr_write4(OCP85XX_LAWSR(i), 0);
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return (0);
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}
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return (ENOENT);
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}
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int
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law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
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{
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u_long start;
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uint32_t ver;
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int trgt, rv;
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ver = SVR_VER(mfspr(SPR_SVR));
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start = rman_get_start(res) & 0xf000;
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rv = 0;
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trgt = -1;
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switch (start) {
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case 0x8000:
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trgt = 0;
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break;
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case 0x9000:
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trgt = 1;
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break;
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case 0xa000:
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
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trgt = 2;
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else
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rv = EINVAL;
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break;
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default:
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rv = ENXIO;
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}
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*trgt_mem = *trgt_io = trgt;
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return (rv);
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}
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void
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cpu_reset(void)
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{
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uint32_t ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
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ver == SVR_MPC8548E || ver == SVR_MPC8548)
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/* Systems with dedicated reset register */
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ccsr_write4(OCP85XX_RSTCR, 2);
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else {
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/* Clear DBCR0, disables debug interrupts and events. */
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mtspr(SPR_DBCR0, 0);
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__asm __volatile("isync");
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/* Enable Debug Interrupts in MSR. */
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mtmsr(mfmsr() | PSL_DE);
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/* Enable debug interrupts and issue reset. */
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mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
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DBCR0_RST_SYSTEM);
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}
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printf("Reset failed...\n");
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while (1);
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}
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