d39a3a978b
After inspecting the ath9k source, it seems the AR5416 and later MACs don't take an explicit RTS/CTS duration. A per-scenario (ie, what multi- rate retry became) rts/cts control flag and packet duration is provided; the hardware then apparently fills in whatever details are required. The per-rate sp/lpack duration calculation just isn't used anywhere in the ath9k TX packet length calculations. The burst duration register controls something different; it seems to be involved with RTS/CTS protection of 11n aggregate frames and is set via a call to ar5416Set11nBurstDuration(). I've done some light testing with rts/cts protected frames and nothing seems to break; but this may break said RTS/CTS and CTS-to-self protection.
728 lines
21 KiB
C
728 lines
21 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_desc.h"
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#include "ah_internal.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ar5416/ar5416desc.h"
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/*
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* Stop transmit on the specified queue
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*/
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HAL_BOOL
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ar5416StopTxDma(struct ath_hal *ah, u_int q)
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{
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#define STOP_DMA_TIMEOUT 4000 /* us */
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#define STOP_DMA_ITER 100 /* us */
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u_int i;
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HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
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HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
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OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
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for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) {
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if (ar5212NumTxPending(ah, q) == 0)
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break;
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OS_DELAY(STOP_DMA_ITER);
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}
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#ifdef AH_DEBUG
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if (i == 0) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: queue %u DMA did not stop in 400 msec\n", __func__, q);
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__,
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OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),
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OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
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__func__, OS_REG_READ(ah, AR_QMISC(q)),
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OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
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OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
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}
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#endif /* AH_DEBUG */
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/* ar5416 and up can kill packets at the PCU level */
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if (ar5212NumTxPending(ah, q)) {
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uint32_t j;
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
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"%s: Num of pending TX Frames %d on Q %d\n",
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__func__, ar5212NumTxPending(ah, q), q);
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/* Kill last PCU Tx Frame */
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/* TODO - save off and restore current values of Q1/Q2? */
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for (j = 0; j < 2; j++) {
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uint32_t tsfLow = OS_REG_READ(ah, AR_TSF_L32);
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OS_REG_WRITE(ah, AR_QUIET2,
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SM(10, AR_QUIET2_QUIET_DUR));
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OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
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OS_REG_WRITE(ah, AR_NEXT_QUIET, tsfLow >> 10);
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OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
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if ((OS_REG_READ(ah, AR_TSF_L32)>>10) == (tsfLow>>10))
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break;
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: TSF moved while trying to set quiet time "
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"TSF: 0x%08x\n", __func__, tsfLow);
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HALASSERT(j < 1); /* TSF shouldn't count twice or reg access is taking forever */
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}
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OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
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/* Allow the quiet mechanism to do its work */
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OS_DELAY(200);
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OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
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/* Verify the transmit q is empty */
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for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) {
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if (ar5212NumTxPending(ah, q) == 0)
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break;
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OS_DELAY(STOP_DMA_ITER);
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}
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if (i == 0) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: Failed to stop Tx DMA in %d msec after killing"
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" last frame\n", __func__, STOP_DMA_TIMEOUT / 1000);
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}
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OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
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}
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OS_REG_WRITE(ah, AR_Q_TXD, 0);
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return (i != 0);
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#undef STOP_DMA_ITER
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#undef STOP_DMA_TIMEOUT
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}
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#define VALID_KEY_TYPES \
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((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\
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(1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP))
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#define isValidKeyType(_t) ((1 << (_t)) & VALID_KEY_TYPES)
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#define set11nTries(_series, _index) \
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(SM((_series)[_index].Tries, AR_XmitDataTries##_index))
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#define set11nRate(_series, _index) \
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(SM((_series)[_index].Rate, AR_XmitRate##_index))
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#define set11nPktDurRTSCTS(_series, _index) \
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(SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
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((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\
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AR_RTSCTSQual##_index : 0))
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#define set11nRateFlags(_series, _index) \
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((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
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|((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \
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|SM((_series)[_index].ChSel, AR_ChainSel##_index)
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/*
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* Descriptor Access Functions
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*/
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#define VALID_PKT_TYPES \
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((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
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(1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
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(1<<HAL_PKT_TYPE_BEACON)|(1<<HAL_PKT_TYPE_AMPDU))
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#define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
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#define VALID_TX_RATES \
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((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
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(1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
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(1<<0x1d)|(1<<0x18)|(1<<0x1c))
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#define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
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HAL_BOOL
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ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
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u_int pktLen,
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u_int hdrLen,
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HAL_PKT_TYPE type,
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u_int txPower,
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u_int txRate0, u_int txTries0,
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u_int keyIx,
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u_int antMode,
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u_int flags,
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u_int rtsctsRate,
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u_int rtsctsDuration,
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u_int compicvLen,
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u_int compivLen,
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u_int comp)
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{
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#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
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struct ar5416_desc *ads = AR5416DESC(ds);
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struct ath_hal_5416 *ahp = AH5416(ah);
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(void) hdrLen;
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HALASSERT(txTries0 != 0);
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HALASSERT(isValidPktType(type));
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HALASSERT(isValidTxRate(txRate0));
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HALASSERT((flags & RTSCTS) != RTSCTS);
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/* XXX validate antMode */
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txPower = (txPower + AH5212(ah)->ah_txPowerIndexOffset);
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if (txPower > 63)
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txPower = 63;
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ads->ds_ctl0 = (pktLen & AR_FrameLen)
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| (txPower << AR_XmitPower_S)
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| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
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| (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
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| (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
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;
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ads->ds_ctl1 = (type << AR_FrameType_S)
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| (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
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;
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ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
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| (flags & HAL_TXDESC_DURENA ? AR_DurUpdateEn : 0)
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;
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ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S)
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;
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ads->ds_ctl4 = 0;
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ads->ds_ctl5 = 0;
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ads->ds_ctl6 = 0;
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ads->ds_ctl7 = SM(ahp->ah_tx_chainmask, AR_ChainSel0)
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| SM(ahp->ah_tx_chainmask, AR_ChainSel1)
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| SM(ahp->ah_tx_chainmask, AR_ChainSel2)
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| SM(ahp->ah_tx_chainmask, AR_ChainSel3)
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;
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ads->ds_ctl8 = 0;
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ads->ds_ctl9 = (txPower << 24); /* XXX? */
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ads->ds_ctl10 = (txPower << 24); /* XXX? */
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ads->ds_ctl11 = (txPower << 24); /* XXX? */
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if (keyIx != HAL_TXKEYIX_INVALID) {
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/* XXX validate key index */
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ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
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ads->ds_ctl0 |= AR_DestIdxValid;
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ads->ds_ctl6 |= SM(ahp->ah_keytype[keyIx], AR_EncrType);
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}
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if (flags & RTSCTS) {
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if (!isValidTxRate(rtsctsRate)) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: invalid rts/cts rate 0x%x\n",
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__func__, rtsctsRate);
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return AH_FALSE;
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}
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/* XXX validate rtsctsDuration */
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ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
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| (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
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;
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ads->ds_ctl7 |= (rtsctsRate << AR_RTSCTSRate_S);
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}
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if (AR_SREV_KITE(ah)) {
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ads->ds_ctl8 = 0;
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ads->ds_ctl9 = 0;
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ads->ds_ctl10 = 0;
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ads->ds_ctl11 = 0;
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}
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return AH_TRUE;
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#undef RTSCTS
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}
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HAL_BOOL
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ar5416SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
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u_int txRate1, u_int txTries1,
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u_int txRate2, u_int txTries2,
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u_int txRate3, u_int txTries3)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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if (txTries1) {
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HALASSERT(isValidTxRate(txRate1));
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ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1);
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ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
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}
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if (txTries2) {
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HALASSERT(isValidTxRate(txRate2));
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ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2);
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ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
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}
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if (txTries3) {
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HALASSERT(isValidTxRate(txRate3));
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ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3);
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ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
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}
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return AH_TRUE;
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}
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HAL_BOOL
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ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
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u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
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const struct ath_desc *ds0)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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HALASSERT((segLen &~ AR_BufLen) == 0);
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if (firstSeg) {
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/*
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* First descriptor, don't clobber xmit control data
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* setup by ar5212SetupTxDesc.
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*/
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ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
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} else if (lastSeg) { /* !firstSeg && lastSeg */
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/*
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* Last descriptor in a multi-descriptor frame,
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* copy the multi-rate transmit parameters from
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* the first frame for processing on completion.
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*/
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 = segLen;
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#ifdef AH_NEED_DESC_SWAP
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ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
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ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
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#else
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ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
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ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
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#endif
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} else { /* !firstSeg && !lastSeg */
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/*
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* Intermediate descriptor in a multi-descriptor frame.
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*/
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 = segLen | AR_TxMore;
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ads->ds_ctl2 = 0;
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ads->ds_ctl3 = 0;
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}
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/* XXX only on last descriptor? */
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OS_MEMZERO(ads->u.tx.status, sizeof(ads->u.tx.status));
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return AH_TRUE;
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}
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HAL_BOOL
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ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds,
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u_int pktLen,
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u_int hdrLen,
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HAL_PKT_TYPE type,
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u_int keyIx,
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HAL_CIPHER cipher,
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uint8_t delims,
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u_int segLen,
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HAL_BOOL firstSeg,
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HAL_BOOL lastSeg)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
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struct ath_hal_5416 *ahp = AH5416(ah);
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int isaggr = 0;
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(void) hdrLen;
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(void) ah;
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HALASSERT((segLen &~ AR_BufLen) == 0);
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HALASSERT(isValidPktType(type));
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if (type == HAL_PKT_TYPE_AMPDU) {
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type = HAL_PKT_TYPE_NORMAL;
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isaggr = 1;
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}
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if (!firstSeg) {
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OS_MEMZERO(ds->ds_hw, AR5416_DESC_TX_CTL_SZ);
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}
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ads->ds_ctl0 = (pktLen & AR_FrameLen);
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ads->ds_ctl1 = (type << AR_FrameType_S)
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| (isaggr ? (AR_IsAggr | AR_MoreAggr) : 0);
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ads->ds_ctl2 = 0;
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ads->ds_ctl3 = 0;
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if (keyIx != HAL_TXKEYIX_INVALID) {
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/* XXX validate key index */
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ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
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ads->ds_ctl0 |= AR_DestIdxValid;
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}
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ads->ds_ctl6 = SM(ahp->ah_keytype[cipher], AR_EncrType);
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if (isaggr) {
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ads->ds_ctl6 |= SM(delims, AR_PadDelim);
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}
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if (firstSeg) {
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ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
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} else if (lastSeg) { /* !firstSeg && lastSeg */
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 |= segLen;
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} else { /* !firstSeg && !lastSeg */
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/*
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* Intermediate descriptor in a multi-descriptor frame.
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*/
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 |= segLen | AR_TxMore;
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}
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ds_txstatus[0] = ds_txstatus[1] = 0;
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ds_txstatus[9] &= ~AR_TxDone;
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return AH_TRUE;
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}
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HAL_BOOL
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ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds,
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u_int aggrLen, u_int flags, u_int txPower,
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u_int txRate0, u_int txTries0, u_int antMode,
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u_int rtsctsRate, u_int rtsctsDuration)
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{
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#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
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struct ar5416_desc *ads = AR5416DESC(ds);
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struct ath_hal_5212 *ahp = AH5212(ah);
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HALASSERT(txTries0 != 0);
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HALASSERT(isValidTxRate(txRate0));
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HALASSERT((flags & RTSCTS) != RTSCTS);
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/* XXX validate antMode */
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txPower = (txPower + ahp->ah_txPowerIndexOffset );
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if(txPower > 63) txPower=63;
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ads->ds_ctl0 |= (txPower << AR_XmitPower_S)
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| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
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| (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
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| (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
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ads->ds_ctl1 |= (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
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ads->ds_ctl2 |= SM(txTries0, AR_XmitDataTries0);
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ads->ds_ctl3 |= (txRate0 << AR_XmitRate0_S);
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ads->ds_ctl7 = SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel0)
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| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel1)
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| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel2)
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| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel3);
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/* NB: no V1 WAR */
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ads->ds_ctl8 = 0;
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ads->ds_ctl9 = (txPower << 24);
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ads->ds_ctl10 = (txPower << 24);
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ads->ds_ctl11 = (txPower << 24);
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ads->ds_ctl6 &= ~(0xffff);
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ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
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|
|
if (flags & RTSCTS) {
|
|
/* XXX validate rtsctsDuration */
|
|
ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
|
|
| (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
|
|
}
|
|
|
|
if (AR_SREV_KITE(ah)) {
|
|
ads->ds_ctl8 = 0;
|
|
ads->ds_ctl9 = 0;
|
|
ads->ds_ctl10 = 0;
|
|
ads->ds_ctl11 = 0;
|
|
}
|
|
|
|
return AH_TRUE;
|
|
#undef RTSCTS
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
|
const struct ath_desc *ds0)
|
|
{
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
|
|
|
ads->ds_ctl1 &= ~AR_MoreAggr;
|
|
ads->ds_ctl6 &= ~AR_PadDelim;
|
|
|
|
/* hack to copy rate info to last desc for later processing */
|
|
#ifdef AH_NEED_DESC_SWAP
|
|
ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
|
|
ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
|
|
#else
|
|
ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
|
|
ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
|
|
#endif
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|
|
#ifdef AH_NEED_DESC_SWAP
|
|
/* Swap transmit descriptor */
|
|
static __inline void
|
|
ar5416SwapTxDesc(struct ath_desc *ds)
|
|
{
|
|
ds->ds_data = __bswap32(ds->ds_data);
|
|
ds->ds_ctl0 = __bswap32(ds->ds_ctl0);
|
|
ds->ds_ctl1 = __bswap32(ds->ds_ctl1);
|
|
ds->ds_hw[0] = __bswap32(ds->ds_hw[0]);
|
|
ds->ds_hw[1] = __bswap32(ds->ds_hw[1]);
|
|
ds->ds_hw[2] = __bswap32(ds->ds_hw[2]);
|
|
ds->ds_hw[3] = __bswap32(ds->ds_hw[3]);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Processing of HW TX descriptor.
|
|
*/
|
|
HAL_STATUS
|
|
ar5416ProcTxDesc(struct ath_hal *ah,
|
|
struct ath_desc *ds, struct ath_tx_status *ts)
|
|
{
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
|
uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
|
|
|
|
#ifdef AH_NEED_DESC_SWAP
|
|
if ((ds_txstatus[9] & __bswap32(AR_TxDone)) == 0)
|
|
return HAL_EINPROGRESS;
|
|
ar5416SwapTxDesc(ds);
|
|
#else
|
|
if ((ds_txstatus[9] & AR_TxDone) == 0)
|
|
return HAL_EINPROGRESS;
|
|
#endif
|
|
|
|
/* Update software copies of the HW status */
|
|
ts->ts_seqnum = MS(ds_txstatus[9], AR_SeqNum);
|
|
ts->ts_tstamp = AR_SendTimestamp(ds_txstatus);
|
|
|
|
ts->ts_status = 0;
|
|
if (ds_txstatus[1] & AR_ExcessiveRetries)
|
|
ts->ts_status |= HAL_TXERR_XRETRY;
|
|
if (ds_txstatus[1] & AR_Filtered)
|
|
ts->ts_status |= HAL_TXERR_FILT;
|
|
if (ds_txstatus[1] & AR_FIFOUnderrun)
|
|
ts->ts_status |= HAL_TXERR_FIFO;
|
|
if (ds_txstatus[9] & AR_TxOpExceeded)
|
|
ts->ts_status |= HAL_TXERR_XTXOP;
|
|
if (ds_txstatus[1] & AR_TxTimerExpired)
|
|
ts->ts_status |= HAL_TXERR_TIMER_EXPIRED;
|
|
|
|
ts->ts_flags = 0;
|
|
if (ds_txstatus[0] & AR_TxBaStatus) {
|
|
ts->ts_flags |= HAL_TX_BA;
|
|
ts->ts_ba_low = AR_BaBitmapLow(ds_txstatus);
|
|
ts->ts_ba_high = AR_BaBitmapHigh(ds_txstatus);
|
|
}
|
|
if (ds->ds_ctl1 & AR_IsAggr)
|
|
ts->ts_flags |= HAL_TX_AGGR;
|
|
if (ds_txstatus[1] & AR_DescCfgErr)
|
|
ts->ts_flags |= HAL_TX_DESC_CFG_ERR;
|
|
if (ds_txstatus[1] & AR_TxDataUnderrun)
|
|
ts->ts_flags |= HAL_TX_DATA_UNDERRUN;
|
|
if (ds_txstatus[1] & AR_TxDelimUnderrun)
|
|
ts->ts_flags |= HAL_TX_DELIM_UNDERRUN;
|
|
|
|
/*
|
|
* Extract the transmit rate used and mark the rate as
|
|
* ``alternate'' if it wasn't the series 0 rate.
|
|
*/
|
|
ts->ts_finaltsi = MS(ds_txstatus[9], AR_FinalTxIdx);
|
|
switch (ts->ts_finaltsi) {
|
|
case 0:
|
|
ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
|
|
break;
|
|
case 1:
|
|
ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1);
|
|
break;
|
|
case 2:
|
|
ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2);
|
|
break;
|
|
case 3:
|
|
ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3);
|
|
break;
|
|
}
|
|
|
|
ts->ts_rssi = MS(ds_txstatus[5], AR_TxRSSICombined);
|
|
ts->ts_rssi_ctl[0] = MS(ds_txstatus[0], AR_TxRSSIAnt00);
|
|
ts->ts_rssi_ctl[1] = MS(ds_txstatus[0], AR_TxRSSIAnt01);
|
|
ts->ts_rssi_ctl[2] = MS(ds_txstatus[0], AR_TxRSSIAnt02);
|
|
ts->ts_rssi_ext[0] = MS(ds_txstatus[5], AR_TxRSSIAnt10);
|
|
ts->ts_rssi_ext[1] = MS(ds_txstatus[5], AR_TxRSSIAnt11);
|
|
ts->ts_rssi_ext[2] = MS(ds_txstatus[5], AR_TxRSSIAnt12);
|
|
ts->ts_evm0 = AR_TxEVM0(ds_txstatus);
|
|
ts->ts_evm1 = AR_TxEVM1(ds_txstatus);
|
|
ts->ts_evm2 = AR_TxEVM2(ds_txstatus);
|
|
|
|
ts->ts_shortretry = MS(ds_txstatus[1], AR_RTSFailCnt);
|
|
ts->ts_longretry = MS(ds_txstatus[1], AR_DataFailCnt);
|
|
/*
|
|
* The retry count has the number of un-acked tries for the
|
|
* final series used. When doing multi-rate retry we must
|
|
* fixup the retry count by adding in the try counts for
|
|
* each series that was fully-processed. Beware that this
|
|
* takes values from the try counts in the final descriptor.
|
|
* These are not required by the hardware. We assume they
|
|
* are placed there by the driver as otherwise we have no
|
|
* access and the driver can't do the calculation because it
|
|
* doesn't know the descriptor format.
|
|
*/
|
|
switch (ts->ts_finaltsi) {
|
|
case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
|
|
case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
|
|
case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
|
|
}
|
|
|
|
/*
|
|
* These fields are not used. Zero these to preserve compatability
|
|
* with existing drivers.
|
|
*/
|
|
ts->ts_virtcol = MS(ads->ds_ctl1, AR_VirtRetryCnt);
|
|
ts->ts_antenna = 0; /* We don't switch antennas on Owl*/
|
|
|
|
/* handle tx trigger level changes internally */
|
|
if ((ts->ts_status & HAL_TXERR_FIFO) ||
|
|
(ts->ts_flags & (HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN)))
|
|
ar5212UpdateTxTrigLevel(ah, AH_TRUE);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
|
|
if (tu > 0xFFFF) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad global tx timeout %u\n",
|
|
__func__, tu);
|
|
/* restore default handling */
|
|
ahp->ah_globaltxtimeout = (u_int) -1;
|
|
return AH_FALSE;
|
|
}
|
|
OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
|
|
ahp->ah_globaltxtimeout = tu;
|
|
return AH_TRUE;
|
|
}
|
|
|
|
u_int
|
|
ar5416GetGlobalTxTimeout(struct ath_hal *ah)
|
|
{
|
|
return MS(OS_REG_READ(ah, AR_GTXTO), AR_GTXTO_TIMEOUT_LIMIT);
|
|
}
|
|
|
|
void
|
|
ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds,
|
|
u_int durUpdateEn, u_int rtsctsRate,
|
|
HAL_11N_RATE_SERIES series[], u_int nseries, u_int flags)
|
|
{
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
|
uint32_t ds_ctl0;
|
|
|
|
HALASSERT(nseries == 4);
|
|
(void)nseries;
|
|
|
|
/*
|
|
* Only one of RTS and CTS enable must be set.
|
|
* If a frame has both set, just do RTS protection -
|
|
* that's enough to satisfy legacy protection.
|
|
*/
|
|
if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
|
|
ds_ctl0 = ads->ds_ctl0;
|
|
|
|
if (flags & HAL_TXDESC_RTSENA) {
|
|
ds_ctl0 &= ~AR_CTSEnable;
|
|
ds_ctl0 |= AR_RTSEnable;
|
|
} else {
|
|
ds_ctl0 &= ~AR_RTSEnable;
|
|
ds_ctl0 |= AR_CTSEnable;
|
|
}
|
|
|
|
ads->ds_ctl0 = ds_ctl0;
|
|
} else {
|
|
ads->ds_ctl0 =
|
|
(ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
|
|
}
|
|
|
|
|
|
ads->ds_ctl2 = set11nTries(series, 0)
|
|
| set11nTries(series, 1)
|
|
| set11nTries(series, 2)
|
|
| set11nTries(series, 3)
|
|
| (durUpdateEn ? AR_DurUpdateEn : 0);
|
|
|
|
ads->ds_ctl3 = set11nRate(series, 0)
|
|
| set11nRate(series, 1)
|
|
| set11nRate(series, 2)
|
|
| set11nRate(series, 3);
|
|
|
|
ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
|
|
| set11nPktDurRTSCTS(series, 1);
|
|
|
|
ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
|
|
| set11nPktDurRTSCTS(series, 3);
|
|
|
|
ads->ds_ctl7 = set11nRateFlags(series, 0)
|
|
| set11nRateFlags(series, 1)
|
|
| set11nRateFlags(series, 2)
|
|
| set11nRateFlags(series, 3)
|
|
| SM(rtsctsRate, AR_RTSCTSRate);
|
|
}
|
|
|
|
void
|
|
ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims)
|
|
{
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
|
uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
|
|
|
|
ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
|
|
|
|
ads->ds_ctl6 &= ~AR_PadDelim;
|
|
ads->ds_ctl6 |= SM(numDelims, AR_PadDelim);
|
|
ads->ds_ctl6 &= ~AR_AggrLen;
|
|
|
|
/*
|
|
* Clear the TxDone status here, may need to change
|
|
* func name to reflect this
|
|
*/
|
|
ds_txstatus[9] &= ~AR_TxDone;
|
|
}
|
|
|
|
void
|
|
ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds)
|
|
{
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
|
|
|
ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
|
|
ads->ds_ctl6 &= ~AR_PadDelim;
|
|
ads->ds_ctl6 &= ~AR_AggrLen;
|
|
}
|
|
|
|
void
|
|
ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds,
|
|
u_int burstDuration)
|
|
{
|
|
struct ar5416_desc *ads = AR5416DESC(ds);
|
|
|
|
ads->ds_ctl2 &= ~AR_BurstDur;
|
|
ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
|
|
}
|
|
|
|
/*
|
|
* Retrieve the rate table from the given TX completion descriptor
|
|
*/
|
|
HAL_BOOL
|
|
ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
|
|
{
|
|
const struct ar5416_desc *ads = AR5416DESC_CONST(ds0);
|
|
|
|
rates[0] = MS(ads->ds_ctl3, AR_XmitRate0);
|
|
rates[1] = MS(ads->ds_ctl3, AR_XmitRate1);
|
|
rates[2] = MS(ads->ds_ctl3, AR_XmitRate2);
|
|
rates[3] = MS(ads->ds_ctl3, AR_XmitRate3);
|
|
|
|
tries[0] = MS(ads->ds_ctl2, AR_XmitDataTries0);
|
|
tries[1] = MS(ads->ds_ctl2, AR_XmitDataTries1);
|
|
tries[2] = MS(ads->ds_ctl2, AR_XmitDataTries2);
|
|
tries[3] = MS(ads->ds_ctl2, AR_XmitDataTries3);
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|