79d6ca331e
Status and Control register at port 0x61. Be more conservative about "catching up" callouts that were supposed to fire in the past by skipping an interrupt if it was scheduled too far in the past. Restore the PIT ACPI DSDT entries and add an entry for NMISC too. Approved by: neel (co-mentor)
367 lines
8.3 KiB
C
367 lines
8.3 KiB
C
/*-
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <machine/vmm.h>
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#include <machine/vmm_dev.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <vmmapi.h>
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#include "acpi.h"
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#include "inout.h"
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#include "pci_emul.h"
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#include "pci_lpc.h"
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#include "uart_emul.h"
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#define IO_ICU1 0x20
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#define IO_ICU2 0xA0
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SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
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SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
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#define ELCR_PORT 0x4d0
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SYSRES_IO(ELCR_PORT, 2);
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#define IO_TIMER1_PORT 0x40
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#define NMISC_PORT 0x61
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SYSRES_IO(NMISC_PORT, 1);
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static struct pci_devinst *lpc_bridge;
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#define LPC_UART_NUM 2
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static struct lpc_uart_softc {
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struct uart_softc *uart_softc;
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const char *opts;
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int iobase;
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int irq;
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int enabled;
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} lpc_uart_softc[LPC_UART_NUM];
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static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
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/*
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* LPC device configuration is in the following form:
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* <lpc_device_name>[,<options>]
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* For e.g. "com1,stdio"
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*/
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int
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lpc_device_parse(const char *opts)
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{
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int unit, error;
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char *str, *cpy, *lpcdev;
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error = -1;
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str = cpy = strdup(opts);
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lpcdev = strsep(&str, ",");
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if (lpcdev != NULL) {
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for (unit = 0; unit < LPC_UART_NUM; unit++) {
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if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
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lpc_uart_softc[unit].opts = str;
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error = 0;
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goto done;
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}
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}
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}
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done:
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if (error)
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free(cpy);
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return (error);
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}
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static void
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lpc_uart_intr_assert(void *arg)
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{
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struct lpc_uart_softc *sc = arg;
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assert(sc->irq >= 0);
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vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
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}
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static void
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lpc_uart_intr_deassert(void *arg)
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{
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/*
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* The COM devices on the LPC bus generate edge triggered interrupts,
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* so nothing more to do here.
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*/
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}
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static int
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lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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int offset;
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struct lpc_uart_softc *sc = arg;
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offset = port - sc->iobase;
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switch (bytes) {
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case 1:
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if (in)
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*eax = uart_read(sc->uart_softc, offset);
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else
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uart_write(sc->uart_softc, offset, *eax);
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break;
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case 2:
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if (in) {
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*eax = uart_read(sc->uart_softc, offset);
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*eax |= uart_read(sc->uart_softc, offset + 1) << 8;
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} else {
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uart_write(sc->uart_softc, offset, *eax);
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uart_write(sc->uart_softc, offset + 1, *eax >> 8);
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}
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break;
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default:
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return (-1);
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}
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return (0);
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}
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static int
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lpc_init(void)
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{
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struct lpc_uart_softc *sc;
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struct inout_port iop;
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const char *name;
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int unit, error;
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/* COM1 and COM2 */
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for (unit = 0; unit < LPC_UART_NUM; unit++) {
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sc = &lpc_uart_softc[unit];
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name = lpc_uart_names[unit];
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if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
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fprintf(stderr, "Unable to allocate resources for "
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"LPC device %s\n", name);
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return (-1);
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}
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sc->uart_softc = uart_init(lpc_uart_intr_assert,
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lpc_uart_intr_deassert, sc);
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if (uart_set_backend(sc->uart_softc, sc->opts) != 0) {
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fprintf(stderr, "Unable to initialize backend '%s' "
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"for LPC device %s\n", sc->opts, name);
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return (-1);
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}
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bzero(&iop, sizeof(struct inout_port));
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iop.name = name;
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iop.port = sc->iobase;
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iop.size = UART_IO_BAR_SIZE;
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iop.flags = IOPORT_F_INOUT;
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iop.handler = lpc_uart_io_handler;
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iop.arg = sc;
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error = register_inout(&iop);
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assert(error == 0);
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sc->enabled = 1;
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}
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return (0);
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}
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static void
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pci_lpc_write_dsdt(struct pci_devinst *pi)
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{
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struct lpc_dsdt **ldpp, *ldp;
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dsdt_line("");
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dsdt_line("Device (ISA)");
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dsdt_line("{");
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dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
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dsdt_line(" OperationRegion (P40C, PCI_Config, 0x60, 0x04)");
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dsdt_indent(1);
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SET_FOREACH(ldpp, lpc_dsdt_set) {
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ldp = *ldpp;
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ldp->handler();
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}
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dsdt_line("");
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dsdt_line("Device (PIC)");
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dsdt_line("{");
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dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
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dsdt_line(" Name (_CRS, ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_indent(2);
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dsdt_fixed_ioport(IO_ICU1, 2);
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dsdt_fixed_ioport(IO_ICU2, 2);
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dsdt_fixed_irq(2);
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dsdt_unindent(2);
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dsdt_line(" })");
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dsdt_line("}");
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dsdt_unindent(1);
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dsdt_line("");
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dsdt_line("Device (TIMR)");
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dsdt_line("{");
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dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
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dsdt_line(" Name (_CRS, ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_indent(2);
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dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
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dsdt_fixed_irq(0);
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dsdt_unindent(2);
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dsdt_line(" })");
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dsdt_line("}");
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dsdt_line("}");
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}
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static void
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pci_lpc_sysres_dsdt(void)
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{
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struct lpc_sysres **lspp, *lsp;
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dsdt_line("");
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dsdt_line("Device (SIO)");
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dsdt_line("{");
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dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
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dsdt_line(" Name (_CRS, ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_indent(2);
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SET_FOREACH(lspp, lpc_sysres_set) {
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lsp = *lspp;
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switch (lsp->type) {
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case LPC_SYSRES_IO:
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dsdt_fixed_ioport(lsp->base, lsp->length);
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break;
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case LPC_SYSRES_MEM:
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dsdt_fixed_mem32(lsp->base, lsp->length);
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break;
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}
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}
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dsdt_unindent(2);
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dsdt_line(" })");
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dsdt_line("}");
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}
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LPC_DSDT(pci_lpc_sysres_dsdt);
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static void
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pci_lpc_uart_dsdt(void)
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{
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struct lpc_uart_softc *sc;
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int unit;
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for (unit = 0; unit < LPC_UART_NUM; unit++) {
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sc = &lpc_uart_softc[unit];
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if (!sc->enabled)
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continue;
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dsdt_line("");
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dsdt_line("Device (%s)", lpc_uart_names[unit]);
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dsdt_line("{");
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dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
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dsdt_line(" Name (_UID, %d)", unit + 1);
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dsdt_line(" Name (_CRS, ResourceTemplate ()");
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dsdt_line(" {");
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dsdt_indent(2);
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dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
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dsdt_fixed_irq(sc->irq);
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dsdt_unindent(2);
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dsdt_line(" })");
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dsdt_line("}");
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}
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}
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LPC_DSDT(pci_lpc_uart_dsdt);
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static void
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pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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int baridx, uint64_t offset, int size, uint64_t value)
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{
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}
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uint64_t
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pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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int baridx, uint64_t offset, int size)
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{
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return (0);
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}
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#define LPC_DEV 0x7000
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#define LPC_VENDOR 0x8086
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static int
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pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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{
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/*
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* Do not allow more than one LPC bridge to be configured.
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*/
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if (lpc_bridge != NULL) {
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fprintf(stderr, "Only one LPC bridge is allowed.\n");
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return (-1);
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}
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/*
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* Enforce that the LPC can only be configured on bus 0. This
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* simplifies the ACPI DSDT because it can provide a decode for
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* all legacy i/o ports behind bus 0.
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*/
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if (pi->pi_bus != 0) {
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fprintf(stderr, "LPC bridge can be present only on bus 0.\n");
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return (-1);
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}
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if (lpc_init() != 0)
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return (-1);
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/* initialize config space */
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pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
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pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
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pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
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pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
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lpc_bridge = pi;
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return (0);
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}
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struct pci_devemu pci_de_lpc = {
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.pe_emu = "lpc",
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.pe_init = pci_lpc_init,
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.pe_write_dsdt = pci_lpc_write_dsdt,
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.pe_barwrite = pci_lpc_write,
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.pe_barread = pci_lpc_read
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};
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PCI_EMUL_SET(pci_de_lpc);
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