2e14174893
This patch should remove the need for kldunload of USB controller drivers at suspend and kldload of USB controller drivers at resume. This patch also fixes some build issues in avr32dci.c MFC after: 2 weeks
284 lines
8.8 KiB
C
284 lines
8.8 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* USB Device Port register definitions, copied from ATMEGA documentation
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* provided by ATMEL.
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*/
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#ifndef _ATMEGADCI_H_
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#define _ATMEGADCI_H_
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#define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1)
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#define ATMEGA_OTGTCON 0xF9
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#define ATMEGA_OTGTCON_VALUE(x) ((x) << 0)
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#define ATMEGA_OTGTCON_PAGE(x) ((x) << 5)
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#define ATMEGA_UEINT 0xF4
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#define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */
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#define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */
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#define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */
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#define ATMEGA_UEDATX 0xF1 /* FIFO data */
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#define ATMEGA_UEIENX 0xF0 /* interrupt enable register */
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#define ATMEGA_UEIENX_TXINE (1 << 0)
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#define ATMEGA_UEIENX_STALLEDE (1 << 1)
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#define ATMEGA_UEIENX_RXOUTE (1 << 2)
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#define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */
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#define ATMEGA_UEIENX_NAKOUTE (1 << 4)
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#define ATMEGA_UEIENX_NAKINE (1 << 6)
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#define ATMEGA_UEIENX_FLERRE (1 << 7)
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#define ATMEGA_UESTA1X 0xEF
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#define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */
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#define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */
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#define ATMEGA_UESTA0X 0xEE
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#define ATMEGA_UESTA0X_NBUSYBK (3 << 0)
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#define ATMEGA_UESTA0X_DTSEQ (3 << 2)
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#define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */
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#define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */
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#define ATMEGA_UESTA0X_CFGOK (1 << 7)
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#define ATMEGA_UECFG1X 0xED /* endpoint config register */
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#define ATMEGA_UECFG1X_ALLOC (1 << 1)
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#define ATMEGA_UECFG1X_EPBK0 (0 << 2)
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#define ATMEGA_UECFG1X_EPBK1 (1 << 2)
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#define ATMEGA_UECFG1X_EPBK2 (2 << 2)
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#define ATMEGA_UECFG1X_EPBK3 (3 << 2)
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#define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4)
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#define ATMEGA_UECFG0X 0xEC
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#define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */
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#define ATMEGA_UECFG0X_EPTYPE0 (0 << 6)
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#define ATMEGA_UECFG0X_EPTYPE1 (1 << 6)
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#define ATMEGA_UECFG0X_EPTYPE2 (2 << 6)
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#define ATMEGA_UECFG0X_EPTYPE3 (3 << 6)
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#define ATMEGA_UECONX 0xEB
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#define ATMEGA_UECONX_EPEN (1 << 0)
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#define ATMEGA_UECONX_RSTDT (1 << 3)
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#define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */
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#define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */
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#define ATMEGA_UERST 0xEA /* endpoint reset register */
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#define ATMEGA_UERST_MASK(n) (1 << (n))
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#define ATMEGA_UENUM 0xE9 /* endpoint number */
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#define ATMEGA_UEINTX 0xE8 /* interrupt register */
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#define ATMEGA_UEINTX_TXINI (1 << 0)
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#define ATMEGA_UEINTX_STALLEDI (1 << 1)
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#define ATMEGA_UEINTX_RXOUTI (1 << 2)
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#define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */
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#define ATMEGA_UEINTX_NAKOUTI (1 << 4)
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#define ATMEGA_UEINTX_RWAL (1 << 5)
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#define ATMEGA_UEINTX_NAKINI (1 << 6)
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#define ATMEGA_UEINTX_FIFOCON (1 << 7)
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#define ATMEGA_UDMFN 0xE6
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#define ATMEGA_UDMFN_FNCERR (1 << 4)
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#define ATMEGA_UDFNUMH 0xE5 /* frame number high */
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#define ATMEGA_UDFNUMH_MASK 7
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#define ATMEGA_UDFNUML 0xE4 /* frame number low */
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#define ATMEGA_UDFNUML_MASK 0xFF
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#define ATMEGA_FRAME_MASK 0x7FF
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#define ATMEGA_UDADDR 0xE3 /* USB address */
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#define ATMEGA_UDADDR_MASK 0x7F
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#define ATMEGA_UDADDR_ADDEN (1 << 7)
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#define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */
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#define ATMEGA_UDINT_SUSPE (1 << 0)
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#define ATMEGA_UDINT_MSOFE (1 << 1)
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#define ATMEGA_UDINT_SOFE (1 << 2)
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#define ATMEGA_UDINT_EORSTE (1 << 3)
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#define ATMEGA_UDINT_WAKEUPE (1 << 4)
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#define ATMEGA_UDINT_EORSME (1 << 5)
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#define ATMEGA_UDINT_UPRSME (1 << 6)
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#define ATMEGA_UDINT 0xE1 /* USB device interrupt status */
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#define ATMEGA_UDINT_SUSPI (1 << 0)
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#define ATMEGA_UDINT_MSOFI (1 << 1)
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#define ATMEGA_UDINT_SOFI (1 << 2)
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#define ATMEGA_UDINT_EORSTI (1 << 3)
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#define ATMEGA_UDINT_WAKEUPI (1 << 4)
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#define ATMEGA_UDINT_EORSMI (1 << 5)
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#define ATMEGA_UDINT_UPRSMI (1 << 6)
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#define ATMEGA_UDCON 0xE0 /* USB device connection register */
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#define ATMEGA_UDCON_DETACH (1 << 0)
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#define ATMEGA_UDCON_RMWKUP (1 << 1)
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#define ATMEGA_UDCON_LSM (1 << 2)
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#define ATMEGA_UDCON_RSTCPU (1 << 3)
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#define ATMEGA_OTGINT 0xDF
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#define ATMEGA_OTGCON 0xDD
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#define ATMEGA_OTGCON_VBUSRQC (1 << 0)
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#define ATMEGA_OTGCON_VBUSREQ (1 << 1)
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#define ATMEGA_OTGCON_VBUSHWC (1 << 2)
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#define ATMEGA_OTGCON_SRPSEL (1 << 3)
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#define ATMEGA_OTGCON_SRPREQ (1 << 4)
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#define ATMEGA_OTGCON_HNPREQ (1 << 5)
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#define ATMEGA_USBINT 0xDA
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#define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */
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#define ATMEGA_USBINT_IDI (1 << 1) /* USB ID interrupt */
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#define ATMEGA_USBSTA 0xD9
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#define ATMEGA_USBSTA_VBUS (1 << 0)
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#define ATMEGA_USBSTA_ID (1 << 1)
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#define ATMEGA_USBCON 0xD8
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#define ATMEGA_USBCON_VBUSTE (1 << 0)
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#define ATMEGA_USBCON_IDE (1 << 1)
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#define ATMEGA_USBCON_OTGPADE (1 << 4)
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#define ATMEGA_USBCON_FRZCLK (1 << 5)
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#define ATMEGA_USBCON_USBE (1 << 7)
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#define ATMEGA_UHWCON 0xD7
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#define ATMEGA_UHWCON_UVREGE (1 << 0)
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#define ATMEGA_UHWCON_UVCONE (1 << 4)
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#define ATMEGA_UHWCON_UIDE (1 << 6)
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#define ATMEGA_UHWCON_UIMOD (1 << 7)
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#define ATMEGA_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define ATMEGA_WRITE_1(sc, reg, data) \
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bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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#define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \
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bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
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#define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \
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bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
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/*
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* Maximum number of endpoints supported:
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*/
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#define ATMEGA_EP_MAX 7
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struct atmegadci_td;
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typedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td);
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typedef void (atmegadci_clocks_t)(struct usb_bus *);
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struct atmegadci_td {
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struct atmegadci_td *obj_next;
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atmegadci_cmd_t *func;
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struct usb_page_cache *pc;
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uint32_t offset;
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uint32_t remainder;
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uint16_t max_packet_size;
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uint8_t error:1;
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uint8_t alt_next:1;
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uint8_t short_pkt:1;
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uint8_t support_multi_buffer:1;
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uint8_t did_stall:1;
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uint8_t ep_no:3;
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};
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struct atmegadci_std_temp {
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atmegadci_cmd_t *func;
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struct usb_page_cache *pc;
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struct atmegadci_td *td;
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struct atmegadci_td *td_next;
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uint32_t len;
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uint32_t offset;
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uint16_t max_frame_size;
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uint8_t short_pkt;
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/*
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* short_pkt = 0: transfer should be short terminated
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* short_pkt = 1: transfer should not be short terminated
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*/
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uint8_t setup_alt_next;
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uint8_t did_stall;
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};
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struct atmegadci_config_desc {
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struct usb_config_descriptor confd;
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struct usb_interface_descriptor ifcd;
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struct usb_endpoint_descriptor endpd;
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} __packed;
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union atmegadci_hub_temp {
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uWord wValue;
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struct usb_port_status ps;
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};
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struct atmegadci_flags {
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uint8_t change_connect:1;
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uint8_t change_suspend:1;
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uint8_t status_suspend:1; /* set if suspended */
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uint8_t status_vbus:1; /* set if present */
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uint8_t status_bus_reset:1; /* set if reset complete */
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uint8_t remote_wakeup:1;
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uint8_t self_powered:1;
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uint8_t clocks_off:1;
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uint8_t port_powered:1;
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uint8_t port_enabled:1;
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uint8_t d_pulled_up:1;
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};
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struct atmegadci_softc {
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struct usb_bus sc_bus;
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union atmegadci_hub_temp sc_hub_temp;
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/* must be set by by the bus interface layer */
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atmegadci_clocks_t *sc_clocks_on;
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atmegadci_clocks_t *sc_clocks_off;
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struct usb_device *sc_devices[ATMEGA_MAX_DEVICES];
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struct resource *sc_irq_res;
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void *sc_intr_hdl;
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struct resource *sc_io_res;
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bus_space_tag_t sc_io_tag;
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bus_space_handle_t sc_io_hdl;
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uint8_t sc_rt_addr; /* root hub address */
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uint8_t sc_dv_addr; /* device address */
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uint8_t sc_conf; /* root hub config */
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uint8_t sc_hub_idata[1];
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struct atmegadci_flags sc_flags;
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};
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/* prototypes */
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usb_error_t atmegadci_init(struct atmegadci_softc *sc);
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void atmegadci_uninit(struct atmegadci_softc *sc);
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void atmegadci_interrupt(struct atmegadci_softc *sc);
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#endif /* _ATMEGADCI_H_ */
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