3378bfdb23
OpenWRT's dts files treat RT3050/RT3052/RT3350 within the same SoC dtsi file, so we need to distinguish between the three dynamically, mainly because the bit we use to determine the clock speed on RT3050/RT3052 can actually be floating on RT3350 and RT3350 is always at 320MHz. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5983
62 lines
2.1 KiB
C
62 lines
2.1 KiB
C
/*-
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* Copyright (c) 2016 Stanislav Galabov.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MTK_SYSCTL_H_
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#define _MTK_SYSCTL_H_
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/* System Control */
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#define SYSCTL_CHIPID0_3 0x00
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#define SYSCTL_CHIPID4_7 0x04
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#define SYSCTL_REVID 0x0C
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#define SYSCTL_REVID_MASK 0xFFFF
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#define SYSCTL_MT7621_REV_E 0x0101
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#define SYSCTL_SYSCFG 0x10
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#define SYSCTL_SYSCFG1 0x14
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#define SYSCTL_CLKCFG0 0x2C
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#define SYSCTL_CLKCFG1 0x30
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#define SYSCTL_RSTCTRL 0x34
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#define SYSCTL_GPIOMODE 0x60
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#define SYSCTL_CUR_CLK_STS 0x44
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#define SYSCTL_MT7620_CPLL_CFG0 0x54
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#define SYSCTL_MT7620_CPLL_CFG1 0x58
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#define SYSCFG1_USB_HOST_MODE (1<<10)
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#define RT3350_CHIPID0_3 0x33335452
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extern uint32_t mtk_sysctl_get(uint32_t);
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extern void mtk_sysctl_set(uint32_t, uint32_t);
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extern void mtk_sysctl_clr_set(uint32_t, uint32_t, uint32_t);
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#endif /* _MTK_SYSCTL_H_ */
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