This is done by representing each bus as root PCI device in ACPI. The device implements the _BBN method to return the PCI bus number to the guest OS. Each PCI bus keeps track of the resources that is decodes for devices configured on the bus: i/o, mmio (32-bit) and mmio (64-bit). These windows are advertised to the guest via the _CRS object of the root device. Bus 0 is treated specially since it consumes the I/O ports to access the PCI config space [0xcf8-0xcff]. It also decodes the legacy I/O ports that are consumed by devices on the LPC bus. For this reason the LPC bridge can be configured only on bus 0. The bus number can be specified using the following command line option to bhyve(8): "-s <bus>:<slot>:<func>,<emul>[,<config>]" Discussed with: grehan@ Reviewed by: jhb@
279 lines
7.7 KiB
C
279 lines
7.7 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _PCI_EMUL_H_
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#define _PCI_EMUL_H_
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#include <sys/types.h>
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#include <sys/queue.h>
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#include <sys/kernel.h>
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#include <sys/_pthreadtypes.h>
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#include <dev/pci/pcireg.h>
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#include <assert.h>
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#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
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#define PCIY_RESERVED 0x00
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struct vmctx;
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struct pci_devinst;
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struct memory_region;
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struct pci_devemu {
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char *pe_emu; /* Name of device emulation */
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/* instance creation */
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int (*pe_init)(struct vmctx *, struct pci_devinst *,
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char *opts);
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/* ACPI DSDT enumeration */
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void (*pe_write_dsdt)(struct pci_devinst *);
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/* config space read/write callbacks */
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int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu,
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struct pci_devinst *pi, int offset,
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int bytes, uint32_t val);
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int (*pe_cfgread)(struct vmctx *ctx, int vcpu,
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struct pci_devinst *pi, int offset,
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int bytes, uint32_t *retval);
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/* BAR read/write callbacks */
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void (*pe_barwrite)(struct vmctx *ctx, int vcpu,
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struct pci_devinst *pi, int baridx,
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uint64_t offset, int size, uint64_t value);
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uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu,
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struct pci_devinst *pi, int baridx,
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uint64_t offset, int size);
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};
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#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x);
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enum pcibar_type {
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PCIBAR_NONE,
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PCIBAR_IO,
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PCIBAR_MEM32,
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PCIBAR_MEM64,
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PCIBAR_MEMHI64
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};
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struct pcibar {
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enum pcibar_type type; /* io or memory */
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uint64_t size;
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uint64_t addr;
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};
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#define PI_NAMESZ 40
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struct msix_table_entry {
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uint64_t addr;
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uint32_t msg_data;
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uint32_t vector_control;
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} __packed;
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/*
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* In case the structure is modified to hold extra information, use a define
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* for the size that should be emulated.
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*/
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#define MSIX_TABLE_ENTRY_SIZE 16
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#define MAX_MSIX_TABLE_ENTRIES 2048
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#define PBA_TABLE_ENTRY_SIZE 8
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enum lintr_stat {
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IDLE,
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ASSERTED,
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PENDING
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};
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struct pci_devinst {
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struct pci_devemu *pi_d;
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struct vmctx *pi_vmctx;
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uint8_t pi_bus, pi_slot, pi_func;
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char pi_name[PI_NAMESZ];
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int pi_bar_getsize;
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struct {
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int8_t pin;
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enum lintr_stat state;
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int ioapic_irq;
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pthread_mutex_t lock;
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} pi_lintr;
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struct {
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int enabled;
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uint64_t addr;
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uint64_t msg_data;
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int maxmsgnum;
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} pi_msi;
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struct {
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int enabled;
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int table_bar;
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int pba_bar;
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size_t table_offset;
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int table_count;
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size_t pba_offset;
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size_t pba_size;
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int function_mask;
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struct msix_table_entry *table; /* allocated at runtime */
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} pi_msix;
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void *pi_arg; /* devemu-private data */
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u_char pi_cfgdata[PCI_REGMAX + 1];
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struct pcibar pi_bar[PCI_BARMAX + 1];
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};
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struct msicap {
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uint8_t capid;
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uint8_t nextptr;
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uint16_t msgctrl;
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uint32_t addrlo;
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uint32_t addrhi;
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uint16_t msgdata;
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} __packed;
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struct msixcap {
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uint8_t capid;
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uint8_t nextptr;
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uint16_t msgctrl;
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uint32_t table_info; /* bar index and offset within it */
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uint32_t pba_info; /* bar index and offset within it */
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} __packed;
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struct pciecap {
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uint8_t capid;
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uint8_t nextptr;
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uint16_t pcie_capabilities;
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uint32_t dev_capabilities; /* all devices */
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uint16_t dev_control;
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uint16_t dev_status;
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uint32_t link_capabilities; /* devices with links */
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uint16_t link_control;
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uint16_t link_status;
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uint32_t slot_capabilities; /* ports with slots */
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uint16_t slot_control;
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uint16_t slot_status;
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uint16_t root_control; /* root ports */
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uint16_t root_capabilities;
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uint32_t root_status;
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uint32_t dev_capabilities2; /* all devices */
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uint16_t dev_control2;
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uint16_t dev_status2;
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uint32_t link_capabilities2; /* devices with links */
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uint16_t link_control2;
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uint16_t link_status2;
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uint32_t slot_capabilities2; /* ports with slots */
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uint16_t slot_control2;
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uint16_t slot_status2;
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} __packed;
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typedef void (*pci_lintr_cb)(int b, int s, int pin, int ioapic_irq, void *arg);
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int init_pci(struct vmctx *ctx);
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void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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int bytes, uint32_t val);
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void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
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int bytes, uint32_t val);
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void pci_callback(void);
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int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
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enum pcibar_type type, uint64_t size);
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int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
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uint64_t hostbase, enum pcibar_type type, uint64_t size);
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int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
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int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
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void pci_generate_msi(struct pci_devinst *pi, int msgnum);
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void pci_generate_msix(struct pci_devinst *pi, int msgnum);
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void pci_lintr_assert(struct pci_devinst *pi);
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void pci_lintr_deassert(struct pci_devinst *pi);
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int pci_lintr_request(struct pci_devinst *pi);
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int pci_msi_enabled(struct pci_devinst *pi);
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int pci_msix_enabled(struct pci_devinst *pi);
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int pci_msix_table_bar(struct pci_devinst *pi);
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int pci_msix_pba_bar(struct pci_devinst *pi);
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int pci_msi_msgnum(struct pci_devinst *pi);
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int pci_parse_slot(char *opt);
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void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
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int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
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int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
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uint64_t value);
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uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
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int pci_count_lintr(int bus);
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void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
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void pci_write_dsdt(void);
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static __inline void
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pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
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{
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assert(offset <= PCI_REGMAX);
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*(uint8_t *)(pi->pi_cfgdata + offset) = val;
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}
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static __inline void
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pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
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{
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assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
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*(uint16_t *)(pi->pi_cfgdata + offset) = val;
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}
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static __inline void
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pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
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{
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assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
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*(uint32_t *)(pi->pi_cfgdata + offset) = val;
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}
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static __inline uint8_t
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pci_get_cfgdata8(struct pci_devinst *pi, int offset)
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{
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assert(offset <= PCI_REGMAX);
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return (*(uint8_t *)(pi->pi_cfgdata + offset));
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}
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static __inline uint16_t
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pci_get_cfgdata16(struct pci_devinst *pi, int offset)
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{
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assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
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return (*(uint16_t *)(pi->pi_cfgdata + offset));
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}
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static __inline uint32_t
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pci_get_cfgdata32(struct pci_devinst *pi, int offset)
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{
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assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
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return (*(uint32_t *)(pi->pi_cfgdata + offset));
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}
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#endif /* _PCI_EMUL_H_ */
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