71bf1c4cc5
As with sha256 add support for accelerated sha512 support to libmd on arm64. This depends on clang 13+ to build as this is the first release with the needed intrinsics. Gcc should also support them, however from a currently unknown release. Reviewed by: cem Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D33373
154 lines
4.7 KiB
C
154 lines
4.7 KiB
C
/*-
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* Copyright (c) 2021 The FreeBSD Foundation
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*
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* This software was developed by Andrew Turner under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <arm_neon.h>
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#include "sha512.h"
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#include "sha512c_impl.h"
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void __hidden
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SHA512_Transform_arm64_impl(uint64_t * state,
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const unsigned char block[SHA512_BLOCK_LENGTH], const uint64_t K[80])
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{
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uint64x2_t W[8];
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uint64x2_t S[4];
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uint64x2_t S_start[4];
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uint64x2_t K_tmp, S_tmp;
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int i;
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#define A64_LOAD_W(x) \
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W[x] = vld1q_u64((const uint64_t *)(&block[(x) * 16])); \
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W[x] = vreinterpretq_u64_u8(vrev64q_u8(vreinterpretq_u8_u64(W[x])))
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/* 1. Prepare the first part of the message schedule W. */
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A64_LOAD_W(0);
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A64_LOAD_W(1);
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A64_LOAD_W(2);
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A64_LOAD_W(3);
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A64_LOAD_W(4);
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A64_LOAD_W(5);
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A64_LOAD_W(6);
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A64_LOAD_W(7);
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/* 2. Initialize working variables. */
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S[0] = vld1q_u64(&state[0]);
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S[1] = vld1q_u64(&state[2]);
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S[2] = vld1q_u64(&state[4]);
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S[3] = vld1q_u64(&state[6]);
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S_start[0] = S[0];
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S_start[1] = S[1];
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S_start[2] = S[2];
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S_start[3] = S[3];
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/* 3. Mix. */
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for (i = 0; i < 80; i += 16) {
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/*
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* The schedule array has 4 vectors:
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* ab = S[( 8 - i) % 4]
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* cd = S[( 9 - i) % 4]
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* ef = S[(10 - i) % 4]
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* gh = S[(11 - i) % 4]
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*
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* The following maacro:
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* - Loads the round constants
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* - Add them to schedule words
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* - Rotates the total to switch the order of the two halves
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* so they are in the correct order for gh
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* - Fix the alignment
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* - Extract fg from ef and gh
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* - Extract de from cd and ef
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* - Pass these into the first part of the sha512 calculation
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* to calculate the Sigma 1 and Ch steps
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* - Calculate the Sigma 0 and Maj steps and store to gh
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* - Add the first part to the cd vector
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*/
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#define A64_RNDr(S, W, i, ii) \
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K_tmp = vld1q_u64(K + (i * 2) + ii); \
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K_tmp = vaddq_u64(W[i], K_tmp); \
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K_tmp = vextq_u64(K_tmp, K_tmp, 1); \
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K_tmp = vaddq_u64(K_tmp, S[(11 - i) % 4]); \
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S_tmp = vsha512hq_u64(K_tmp, \
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vextq_u64(S[(10 - i) % 4], S[(11 - i) % 4], 1), \
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vextq_u64(S[(9 - i) % 4], S[(10 - i) % 4], 1)); \
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S[(11 - i) % 4] = vsha512h2q_u64(S_tmp, S[(9 - i) % 4], S[(8 - i) % 4]); \
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S[(9 - i) % 4] = vaddq_u64(S[(9 - i) % 4], S_tmp)
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A64_RNDr(S, W, 0, i);
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A64_RNDr(S, W, 1, i);
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A64_RNDr(S, W, 2, i);
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A64_RNDr(S, W, 3, i);
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A64_RNDr(S, W, 4, i);
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A64_RNDr(S, W, 5, i);
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A64_RNDr(S, W, 6, i);
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A64_RNDr(S, W, 7, i);
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if (i == 64)
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break;
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/*
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* Perform the Message schedule computation:
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* - vsha512su0q_u64 performs the sigma 0 half and add it to
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* the old value
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* - vextq_u64 fixes the alignment of the vectors
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* - vsha512su1q_u64 performs the sigma 1 half and adds it
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* and both the above all together
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*/
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#define A64_MSCH(x) \
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W[x] = vsha512su1q_u64( \
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vsha512su0q_u64(W[x], W[(x + 1) % 8]), \
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W[(x + 7) % 8], \
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vextq_u64(W[(x + 4) % 8], W[(x + 5) % 8], 1))
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A64_MSCH(0);
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A64_MSCH(1);
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A64_MSCH(2);
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A64_MSCH(3);
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A64_MSCH(4);
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A64_MSCH(5);
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A64_MSCH(6);
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A64_MSCH(7);
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}
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/* 4. Mix local working variables into global state */
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S[0] = vaddq_u64(S[0], S_start[0]);
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S[1] = vaddq_u64(S[1], S_start[1]);
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S[2] = vaddq_u64(S[2], S_start[2]);
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S[3] = vaddq_u64(S[3], S_start[3]);
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vst1q_u64(&state[0], S[0]);
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vst1q_u64(&state[2], S[1]);
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vst1q_u64(&state[4], S[2]);
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vst1q_u64(&state[6], S[3]);
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}
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