681 lines
20 KiB
C
681 lines
20 KiB
C
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#ifndef _I915_DRV_H_
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#define _I915_DRV_H_
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#include "dev/drm/drm_mm.h"
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#include "dev/drm/i915_reg.h"
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/* General customization:
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*/
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#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
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#define DRIVER_NAME "i915"
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#define DRIVER_DESC "Intel Graphics"
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#define DRIVER_DATE "20080730"
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enum pipe {
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PIPE_A = 0,
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PIPE_B,
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};
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#define I915_NUM_PIPE 2
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/* Interface history:
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*
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* 1.1: Original.
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* 1.2: Add Power Management
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* 1.3: Add vblank support
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* 1.4: Fix cmdbuffer path, add heap destroy
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* 1.5: Add vblank pipe configuration
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* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
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* - Support vertical blank on secondary display pipe
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 6
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#define DRIVER_PATCHLEVEL 0
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#define WATCH_COHERENCY 0
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#define WATCH_BUF 0
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#define WATCH_EXEC 0
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#define WATCH_LRU 0
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#define WATCH_RELOC 0
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#define WATCH_INACTIVE 0
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#define WATCH_PWRITE 0
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typedef struct _drm_i915_ring_buffer {
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int tail_mask;
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unsigned long Size;
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u8 *virtual_start;
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int head;
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int tail;
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int space;
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drm_local_map_t map;
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struct drm_gem_object *ring_obj;
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} drm_i915_ring_buffer_t;
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struct mem_block {
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struct mem_block *next;
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struct mem_block *prev;
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int start;
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int size;
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struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
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};
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struct opregion_header;
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struct opregion_acpi;
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struct opregion_swsci;
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struct opregion_asle;
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struct intel_opregion {
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struct opregion_header *header;
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struct opregion_acpi *acpi;
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struct opregion_swsci *swsci;
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struct opregion_asle *asle;
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int enabled;
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};
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typedef struct drm_i915_private {
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struct drm_device *dev;
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drm_local_map_t *sarea;
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drm_local_map_t *mmio_map;
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drm_i915_sarea_t *sarea_priv;
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drm_i915_ring_buffer_t ring;
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drm_dma_handle_t *status_page_dmah;
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void *hw_status_page;
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dma_addr_t dma_status_page;
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uint32_t counter;
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unsigned int status_gfx_addr;
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drm_local_map_t hws_map;
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struct drm_gem_object *hws_obj;
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unsigned int cpp;
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int back_offset;
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int front_offset;
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int current_page;
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int page_flipping;
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wait_queue_head_t irq_queue;
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/** Protects user_irq_refcount and irq_mask_reg */
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DRM_SPINTYPE user_irq_lock;
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/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
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int user_irq_refcount;
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/** Cached value of IER to avoid reads in updating the bitfield */
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u32 irq_mask_reg;
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u32 pipestat[2];
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int tex_lru_log_granularity;
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int allow_batchbuffer;
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struct mem_block *agp_heap;
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unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
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int vblank_pipe;
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struct intel_opregion opregion;
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/* Register state */
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u8 saveLBB;
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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u32 saveDSPARB;
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u32 saveRENDERSTANDBY;
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u32 saveHWS;
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u32 savePIPEACONF;
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u32 savePIPEBCONF;
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u32 savePIPEASRC;
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u32 savePIPEBSRC;
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u32 saveFPA0;
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u32 saveFPA1;
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u32 saveDPLL_A;
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u32 saveDPLL_A_MD;
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u32 saveHTOTAL_A;
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u32 saveHBLANK_A;
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u32 saveHSYNC_A;
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u32 saveVTOTAL_A;
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u32 saveVBLANK_A;
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u32 saveVSYNC_A;
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u32 saveBCLRPAT_A;
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u32 savePIPEASTAT;
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u32 saveDSPASTRIDE;
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u32 saveDSPASIZE;
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u32 saveDSPAPOS;
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u32 saveDSPAADDR;
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u32 saveDSPASURF;
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u32 saveDSPATILEOFF;
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u32 savePFIT_PGM_RATIOS;
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u32 saveBLC_PWM_CTL;
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u32 saveBLC_PWM_CTL2;
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u32 saveFPB0;
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u32 saveFPB1;
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u32 saveDPLL_B;
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u32 saveDPLL_B_MD;
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u32 saveHTOTAL_B;
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u32 saveHBLANK_B;
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u32 saveHSYNC_B;
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u32 saveVTOTAL_B;
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u32 saveVBLANK_B;
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u32 saveVSYNC_B;
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u32 saveBCLRPAT_B;
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u32 savePIPEBSTAT;
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u32 saveDSPBSTRIDE;
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u32 saveDSPBSIZE;
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u32 saveDSPBPOS;
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u32 saveDSPBADDR;
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u32 saveDSPBSURF;
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u32 saveDSPBTILEOFF;
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u32 saveVGA0;
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u32 saveVGA1;
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u32 saveVGA_PD;
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u32 saveVGACNTRL;
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u32 saveADPA;
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u32 saveLVDS;
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u32 savePP_ON_DELAYS;
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u32 savePP_OFF_DELAYS;
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u32 saveDVOA;
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u32 saveDVOB;
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u32 saveDVOC;
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u32 savePP_ON;
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u32 savePP_OFF;
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u32 savePP_CONTROL;
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u32 savePP_DIVISOR;
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u32 savePFIT_CONTROL;
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u32 save_palette_a[256];
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u32 save_palette_b[256];
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u32 saveFBC_CFB_BASE;
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u32 saveFBC_LL_BASE;
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u32 saveFBC_CONTROL;
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u32 saveFBC_CONTROL2;
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u32 saveIER;
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u32 saveIIR;
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u32 saveIMR;
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u32 saveCACHE_MODE_0;
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u32 saveD_STATE;
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u32 saveCG_2D_DIS;
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u32 saveMI_ARB_STATE;
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u32 saveSWF0[16];
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u32 saveSWF1[16];
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u32 saveSWF2[3];
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u8 saveMSR;
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u8 saveSR[8];
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u8 saveGR[25];
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u8 saveAR_INDEX;
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u8 saveAR[21];
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u8 saveDACMASK;
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u8 saveCR[37];
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struct {
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struct drm_mm gtt_space;
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/**
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* List of objects currently involved in rendering from the
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* ringbuffer.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* List of objects which are not in the ringbuffer but which
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* still have a write_domain which needs to be flushed before
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* unbinding.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head flushing_list;
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/**
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* LRU list of objects which are not in the ringbuffer and
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* are ready to unbind, but are still in the GTT.
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*
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* A reference is not held on the buffer while on this list,
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* as merely being GTT-bound shouldn't prevent its being
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* freed, and we'll pull it off the list in the free path.
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*/
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struct list_head inactive_list;
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/**
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* List of breadcrumbs associated with GPU requests currently
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* outstanding.
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*/
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struct list_head request_list;
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#ifdef __linux__
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/**
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* We leave the user IRQ off as much as possible,
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* but this means that requests will finish and never
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* be retired once the system goes idle. Set a timer to
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* fire periodically while the ring is running. When it
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* fires, go retire requests.
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*/
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struct delayed_work retire_work;
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#endif
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uint32_t next_gem_seqno;
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/**
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* Waiting sequence number, if any
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*/
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uint32_t waiting_gem_seqno;
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/**
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* Last seq seen at irq time
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*/
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uint32_t irq_gem_seqno;
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/**
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* Flag if the X Server, and thus DRM, is not currently in
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* control of the device.
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*
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* This is set between LeaveVT and EnterVT. It needs to be
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* replaced with a semaphore. It also needs to be
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* transitioned away from for kernel modesetting.
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*/
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int suspended;
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/**
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* Flag if the hardware appears to be wedged.
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*
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* This is set when attempts to idle the device timeout.
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* It prevents command submission from occuring and makes
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* every pending request fail
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*/
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int wedged;
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/** Bit 6 swizzling required for X tiling */
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uint32_t bit_6_swizzle_x;
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/** Bit 6 swizzling required for Y tiling */
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uint32_t bit_6_swizzle_y;
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} mm;
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} drm_i915_private_t;
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enum intel_chip_family {
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CHIP_I8XX = 0x01,
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CHIP_I9XX = 0x02,
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CHIP_I915 = 0x04,
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CHIP_I965 = 0x08,
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};
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/** driver private structure attached to each drm_gem_object */
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struct drm_i915_gem_object {
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struct drm_gem_object *obj;
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/** Current space allocated to this object in the GTT, if any. */
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struct drm_mm_node *gtt_space;
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/** This object's place on the active/flushing/inactive lists */
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struct list_head list;
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/**
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* This is set if the object is on the active or flushing lists
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* (has pending rendering), and is not set if it's on inactive (ready
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* to be unbound).
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*/
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int active;
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/**
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* This is set if the object has been written to since last bound
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* to the GTT
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*/
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int dirty;
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/** AGP memory structure for our GTT binding. */
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DRM_AGP_MEM *agp_mem;
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struct page **page_list;
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/**
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* Current offset of the object in GTT space.
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*
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* This is the same as gtt_space->start
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*/
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uint32_t gtt_offset;
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/** Boolean whether this object has a valid gtt offset. */
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int gtt_bound;
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/** How many users have pinned this object in GTT space */
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int pin_count;
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/** Breadcrumb of last rendering to the buffer. */
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uint32_t last_rendering_seqno;
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/** Current tiling mode for the object. */
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uint32_t tiling_mode;
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/** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
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uint32_t agp_type;
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/**
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* Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
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* GEM_DOMAIN_CPU is not in the object's read domain.
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*/
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uint8_t *page_cpu_valid;
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};
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/**
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* Request queue structure.
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*
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* The request queue allows us to note sequence numbers that have been emitted
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* and may be associated with active buffers to be retired.
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*
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* By keeping this list, we can avoid having to do questionable
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* sequence-number comparisons on buffer last_rendering_seqnos, and associate
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* an emission time with seqnos for tracking how far ahead of the GPU we are.
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*/
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struct drm_i915_gem_request {
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/** GEM sequence number associated with this request. */
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uint32_t seqno;
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/** Time at which this request was emitted, in jiffies. */
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unsigned long emitted_jiffies;
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/** Cache domains that were flushed at the start of the request. */
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uint32_t flush_domains;
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struct list_head list;
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};
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struct drm_i915_file_private {
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struct {
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uint32_t last_gem_seqno;
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uint32_t last_gem_throttle_seqno;
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} mm;
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};
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extern struct drm_ioctl_desc i915_ioctls[];
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extern int i915_max_ioctl;
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/* i915_dma.c */
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extern void i915_kernel_lost_context(struct drm_device * dev);
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extern int i915_driver_load(struct drm_device *, unsigned long flags);
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extern int i915_driver_unload(struct drm_device *);
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extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
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extern void i915_driver_lastclose(struct drm_device * dev);
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extern void i915_driver_preclose(struct drm_device *dev,
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struct drm_file *file_priv);
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extern void i915_driver_postclose(struct drm_device *dev,
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struct drm_file *file_priv);
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extern int i915_driver_device_is_agp(struct drm_device * dev);
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extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
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unsigned long arg);
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extern int i915_emit_box(struct drm_device *dev,
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struct drm_clip_rect __user *boxes,
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int i, int DR1, int DR4);
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/* i915_irq.c */
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extern int i915_irq_emit(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_irq_wait(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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void i915_user_irq_get(struct drm_device *dev);
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void i915_user_irq_put(struct drm_device *dev);
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extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
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extern void i915_driver_irq_preinstall(struct drm_device * dev);
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extern int i915_driver_irq_postinstall(struct drm_device *dev);
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extern void i915_driver_irq_uninstall(struct drm_device * dev);
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extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_enable_vblank(struct drm_device *dev, int crtc);
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extern void i915_disable_vblank(struct drm_device *dev, int crtc);
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extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
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extern u32 g45_get_vblank_counter(struct drm_device *dev, int crtc);
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extern int i915_vblank_swap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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void
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i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
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void
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i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
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/* i915_mem.c */
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extern int i915_mem_alloc(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_mem_free(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_mem_init_heap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern void i915_mem_takedown(struct mem_block **heap);
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extern void i915_mem_release(struct drm_device * dev,
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struct drm_file *file_priv, struct mem_block *heap);
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#ifdef I915_HAVE_GEM
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/* i915_gem.c */
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int i915_gem_init_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_create_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_execbuffer(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
|
|
int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_set_tiling(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_get_tiling(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
void i915_gem_load(struct drm_device *dev);
|
|
int i915_gem_proc_init(struct drm_minor *minor);
|
|
void i915_gem_proc_cleanup(struct drm_minor *minor);
|
|
int i915_gem_init_object(struct drm_gem_object *obj);
|
|
void i915_gem_free_object(struct drm_gem_object *obj);
|
|
int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
|
|
void i915_gem_object_unpin(struct drm_gem_object *obj);
|
|
void i915_gem_lastclose(struct drm_device *dev);
|
|
uint32_t i915_get_gem_seqno(struct drm_device *dev);
|
|
void i915_gem_retire_requests(struct drm_device *dev);
|
|
void i915_gem_retire_work_handler(struct work_struct *work);
|
|
void i915_gem_clflush_object(struct drm_gem_object *obj);
|
|
|
|
/* i915_gem_tiling.c */
|
|
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
|
|
|
|
/* i915_gem_debug.c */
|
|
void i915_gem_dump_object(struct drm_gem_object *obj, int len,
|
|
const char *where, uint32_t mark);
|
|
#if WATCH_INACTIVE
|
|
void i915_verify_inactive(struct drm_device *dev, char *file, int line);
|
|
#else
|
|
#define i915_verify_inactive(dev, file, line)
|
|
#endif
|
|
void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
|
|
void i915_gem_dump_object(struct drm_gem_object *obj, int len,
|
|
const char *where, uint32_t mark);
|
|
void i915_dump_lru(struct drm_device *dev, const char *where);
|
|
#endif /* I915_HAVE_GEM */
|
|
|
|
/* i915_suspend.c */
|
|
extern int i915_save_state(struct drm_device *dev);
|
|
extern int i915_restore_state(struct drm_device *dev);
|
|
|
|
/* i915_opregion.c */
|
|
extern int intel_opregion_init(struct drm_device *dev);
|
|
extern void intel_opregion_free(struct drm_device *dev);
|
|
extern void opregion_asle_intr(struct drm_device *dev);
|
|
extern void opregion_enable_asle(struct drm_device *dev);
|
|
|
|
/**
|
|
* Lock test for when it's just for synchronization of ring access.
|
|
*
|
|
* In that case, we don't need to do it when GEM is initialized as nobody else
|
|
* has access to the ring.
|
|
*/
|
|
#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
|
|
if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv); \
|
|
} while (0)
|
|
|
|
#if defined(__FreeBSD__)
|
|
typedef boolean_t bool;
|
|
#endif
|
|
|
|
#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
|
|
#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
|
|
#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
|
|
#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
|
|
#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg))
|
|
#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val))
|
|
|
|
#define I915_VERBOSE 0
|
|
|
|
#define RING_LOCALS unsigned int outring, ringmask, outcount; \
|
|
volatile char *virt;
|
|
|
|
#define BEGIN_LP_RING(n) do { \
|
|
if (I915_VERBOSE) \
|
|
DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
|
|
if (dev_priv->ring.space < (n)*4) \
|
|
i915_wait_ring(dev, (n)*4, __func__); \
|
|
outcount = 0; \
|
|
outring = dev_priv->ring.tail; \
|
|
ringmask = dev_priv->ring.tail_mask; \
|
|
virt = dev_priv->ring.virtual_start; \
|
|
} while (0)
|
|
|
|
#define OUT_RING(n) do { \
|
|
if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
|
|
*(volatile unsigned int *)(virt + outring) = (n); \
|
|
outcount++; \
|
|
outring += 4; \
|
|
outring &= ringmask; \
|
|
} while (0)
|
|
|
|
#define ADVANCE_LP_RING() do { \
|
|
if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
|
|
dev_priv->ring.tail = outring; \
|
|
dev_priv->ring.space -= outcount * 4; \
|
|
I915_WRITE(PRB0_TAIL, outring); \
|
|
} while(0)
|
|
|
|
/**
|
|
* Reads a dword out of the status page, which is written to from the command
|
|
* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
|
|
* MI_STORE_DATA_IMM.
|
|
*
|
|
* The following dwords have a reserved meaning:
|
|
* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
|
|
* 0x04: ring 0 head pointer
|
|
* 0x05: ring 1 head pointer (915-class)
|
|
* 0x06: ring 2 head pointer (915-class)
|
|
* 0x10-0x1b: Context status DWords (GM45)
|
|
* 0x1f: Last written status offset. (GM45)
|
|
*
|
|
* The area from dword 0x20 to 0x3ff is available for driver usage.
|
|
*/
|
|
#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
|
|
#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
|
|
#define I915_GEM_HWS_INDEX 0x20
|
|
#define I915_BREADCRUMB_INDEX 0x21
|
|
|
|
extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
|
|
|
|
#define IS_I830(dev) ((dev)->pci_device == 0x3577)
|
|
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
|
|
#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
|
|
#define IS_I855(dev) ((dev)->pci_device == 0x3582)
|
|
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
|
|
|
|
#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
|
|
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
|
|
#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
|
|
#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
|
|
(dev)->pci_device == 0x27AE)
|
|
#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
|
|
(dev)->pci_device == 0x2982 || \
|
|
(dev)->pci_device == 0x2992 || \
|
|
(dev)->pci_device == 0x29A2 || \
|
|
(dev)->pci_device == 0x2A02 || \
|
|
(dev)->pci_device == 0x2A12 || \
|
|
(dev)->pci_device == 0x2A42 || \
|
|
(dev)->pci_device == 0x2E02 || \
|
|
(dev)->pci_device == 0x2E12 || \
|
|
(dev)->pci_device == 0x2E22 || \
|
|
(dev)->pci_device == 0x2E32)
|
|
|
|
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
|
|
|
|
#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
|
|
|
|
#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
|
|
(dev)->pci_device == 0x2E12 || \
|
|
(dev)->pci_device == 0x2E22 || \
|
|
(dev)->pci_device == 0x2E32 || \
|
|
IS_GM45(dev))
|
|
|
|
#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
|
|
#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
|
|
#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
|
|
|
|
#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
|
|
(dev)->pci_device == 0x29B2 || \
|
|
(dev)->pci_device == 0x29D2 || \
|
|
IS_IGD(dev))
|
|
|
|
#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
|
|
IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
|
|
|
|
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
|
|
IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
|
|
IS_IGD(dev))
|
|
|
|
#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
|
|
|
|
#define PRIMARY_RINGBUFFER_SIZE (128*1024)
|
|
|
|
#endif
|