472 lines
10 KiB
C
472 lines
10 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Vybrid Family Inter-Integrated Circuit (I2C)
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* Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013
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*/
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/*
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* This driver is based on the I2C driver for i.MX
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/freescale/vybrid/vf_common.h>
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#define I2C_IBAD 0x0 /* I2C Bus Address Register */
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#define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */
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#define I2C_IBCR 0x2 /* I2C Bus Control Register */
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#define IBCR_MDIS (1 << 7) /* Module disable. */
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#define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */
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#define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */
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#define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */
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#define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */
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#define IBCR_RSTA (1 << 2) /* Repeat Start. */
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#define IBCR_DMAEN (1 << 1) /* DMA Enable. */
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#define I2C_IBSR 0x3 /* I2C Bus Status Register */
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#define IBSR_TCF (1 << 7) /* Transfer complete. */
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#define IBSR_IAAS (1 << 6) /* Addressed as a slave. */
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#define IBSR_IBB (1 << 5) /* Bus busy. */
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#define IBSR_IBAL (1 << 4) /* Arbitration Lost. */
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#define IBSR_SRW (1 << 2) /* Slave Read/Write. */
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#define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */
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#define IBSR_RXAK (1 << 0) /* Received Acknowledge. */
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#define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */
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#define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */
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#define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */
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#define I2C_IBDBG 0x6 /* I2C Bus Debug Register */
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#ifdef DEBUG
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#define vf_i2c_dbg(_sc, fmt, args...) \
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device_printf((_sc)->dev, fmt, ##args)
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#else
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#define vf_i2c_dbg(_sc, fmt, args...)
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#endif
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static int i2c_repeated_start(device_t, u_char, int);
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static int i2c_start(device_t, u_char, int);
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static int i2c_stop(device_t);
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static int i2c_reset(device_t, u_char, u_char, u_char *);
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static int i2c_read(device_t, char *, int, int *, int, int);
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static int i2c_write(device_t, const char *, int, int *, int);
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struct i2c_softc {
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struct resource *res[2];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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device_t iicbus;
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struct mtx mutex;
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};
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static struct resource_spec i2c_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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i2c_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,mvf600-i2c"))
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return (ENXIO);
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device_set_desc(dev, "Vybrid Family Inter-Integrated Circuit (I2C)");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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i2c_attach(device_t dev)
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{
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struct i2c_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
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if (bus_alloc_resources(dev, i2c_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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WRITE1(sc, I2C_IBIC, IBIC_BIIE);
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sc->iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->iicbus == NULL) {
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device_printf(dev, "could not add iicbus child");
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mtx_destroy(&sc->mutex);
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return (ENXIO);
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}
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bus_generic_attach(dev);
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return (0);
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}
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/* Wait for transfer interrupt flag */
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static int
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wait_for_iif(struct i2c_softc *sc)
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{
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int retry;
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retry = 1000;
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while (retry --) {
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if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
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WRITE1(sc, I2C_IBSR, IBSR_IBIF);
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return (IIC_NOERR);
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}
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DELAY(10);
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}
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return (IIC_ETIMEOUT);
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}
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/* Wait for free bus */
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static int
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wait_for_nibb(struct i2c_softc *sc)
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{
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int retry;
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retry = 1000;
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while (retry --) {
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if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0)
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return (IIC_NOERR);
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DELAY(10);
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}
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return (IIC_ETIMEOUT);
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}
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/* Wait for transfer complete+interrupt flag */
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static int
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wait_for_icf(struct i2c_softc *sc)
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{
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int retry;
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retry = 1000;
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while (retry --) {
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if (READ1(sc, I2C_IBSR) & IBSR_TCF) {
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if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
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WRITE1(sc, I2C_IBSR, IBSR_IBIF);
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return (IIC_NOERR);
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}
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}
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DELAY(10);
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}
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return (IIC_ETIMEOUT);
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}
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static int
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i2c_repeated_start(device_t dev, u_char slave, int timeout)
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{
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struct i2c_softc *sc;
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int error;
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int reg;
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sc = device_get_softc(dev);
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vf_i2c_dbg(sc, "i2c repeated start\n");
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mtx_lock(&sc->mutex);
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WRITE1(sc, I2C_IBAD, slave);
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if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) {
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mtx_unlock(&sc->mutex);
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return (IIC_EBUSBSY);
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}
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/* Set repeated start condition */
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DELAY(10);
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reg = READ1(sc, I2C_IBCR);
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reg |= (IBCR_RSTA | IBCR_IBIE);
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WRITE1(sc, I2C_IBCR, reg);
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DELAY(10);
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/* Write target address - LSB is R/W bit */
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WRITE1(sc, I2C_IBDR, slave);
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error = wait_for_iif(sc);
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mtx_unlock(&sc->mutex);
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if (error)
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return (error);
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return (IIC_NOERR);
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}
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static int
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i2c_start(device_t dev, u_char slave, int timeout)
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{
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struct i2c_softc *sc;
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int error;
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int reg;
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sc = device_get_softc(dev);
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vf_i2c_dbg(sc, "i2c start\n");
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mtx_lock(&sc->mutex);
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WRITE1(sc, I2C_IBAD, slave);
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if (READ1(sc, I2C_IBSR) & IBSR_IBB) {
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mtx_unlock(&sc->mutex);
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vf_i2c_dbg(sc, "cant i2c start: IIC_EBUSBSY\n");
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return (IIC_EBUSBSY);
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}
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/* Set start condition */
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reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE);
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WRITE1(sc, I2C_IBCR, reg);
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DELAY(100);
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reg |= (IBCR_TXRX);
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WRITE1(sc, I2C_IBCR, reg);
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/* Write target address - LSB is R/W bit */
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WRITE1(sc, I2C_IBDR, slave);
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error = wait_for_iif(sc);
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mtx_unlock(&sc->mutex);
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if (error) {
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vf_i2c_dbg(sc, "cant i2c start: iif error\n");
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return (error);
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}
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return (IIC_NOERR);
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}
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static int
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i2c_stop(device_t dev)
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{
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struct i2c_softc *sc;
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sc = device_get_softc(dev);
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vf_i2c_dbg(sc, "i2c stop\n");
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mtx_lock(&sc->mutex);
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WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE);
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DELAY(100);
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/* Reset controller if bus still busy after STOP */
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if (wait_for_nibb(sc) == IIC_ETIMEOUT) {
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WRITE1(sc, I2C_IBCR, IBCR_MDIS);
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DELAY(1000);
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WRITE1(sc, I2C_IBCR, IBCR_NOACK);
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}
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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static int
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i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
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{
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struct i2c_softc *sc;
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sc = device_get_softc(dev);
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vf_i2c_dbg(sc, "i2c reset\n");
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switch (speed) {
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case IIC_FAST:
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case IIC_SLOW:
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case IIC_UNKNOWN:
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case IIC_FASTEST:
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default:
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break;
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}
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mtx_lock(&sc->mutex);
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WRITE1(sc, I2C_IBCR, IBCR_MDIS);
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DELAY(1000);
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WRITE1(sc, I2C_IBFD, 20);
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WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */
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DELAY(1000);
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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static int
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i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
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{
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struct i2c_softc *sc;
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int error;
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sc = device_get_softc(dev);
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vf_i2c_dbg(sc, "i2c read\n");
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*read = 0;
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mtx_lock(&sc->mutex);
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if (len) {
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if (len == 1)
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WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \
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IBCR_NOACK);
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else
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WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL);
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/* dummy read */
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READ1(sc, I2C_IBDR);
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DELAY(1000);
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}
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while (*read < len) {
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error = wait_for_icf(sc);
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if (error) {
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mtx_unlock(&sc->mutex);
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return (error);
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}
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if ((*read == len - 2) && last) {
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/* NO ACK on last byte */
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WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \
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IBCR_NOACK);
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}
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if ((*read == len - 1) && last) {
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/* Transfer done, remove master bit */
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WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK);
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}
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*buf++ = READ1(sc, I2C_IBDR);
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(*read)++;
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}
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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static int
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i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
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{
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struct i2c_softc *sc;
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int error;
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sc = device_get_softc(dev);
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vf_i2c_dbg(sc, "i2c write\n");
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*sent = 0;
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mtx_lock(&sc->mutex);
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while (*sent < len) {
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WRITE1(sc, I2C_IBDR, *buf++);
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error = wait_for_iif(sc);
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if (error) {
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mtx_unlock(&sc->mutex);
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return (error);
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}
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(*sent)++;
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}
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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static device_method_t i2c_methods[] = {
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DEVMETHOD(device_probe, i2c_probe),
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DEVMETHOD(device_attach, i2c_attach),
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DEVMETHOD(iicbus_callback, iicbus_null_callback),
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DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
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DEVMETHOD(iicbus_start, i2c_start),
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DEVMETHOD(iicbus_stop, i2c_stop),
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DEVMETHOD(iicbus_reset, i2c_reset),
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DEVMETHOD(iicbus_read, i2c_read),
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DEVMETHOD(iicbus_write, i2c_write),
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DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
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{ 0, 0 }
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};
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static driver_t i2c_driver = {
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"i2c",
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i2c_methods,
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sizeof(struct i2c_softc),
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};
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static devclass_t i2c_devclass;
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DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
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DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
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