a5eb009b49
Poll for link state when the link is down, even for interrupt capable PHYs. Allow PHYs to report a dubious "partial" link. If this state is seen 3 consecutive times (each check is ~1s apart) then reset the PHY. This is a workaround for a situation where repeatedly toggling the link from the peer gets the AEL2005 PHY into a state where it never establishes a PCS block lock even when everything is in order. MFC after: 1 week
318 lines
9.7 KiB
C
318 lines
9.7 KiB
C
/**************************************************************************
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Copyright (c) 2007, Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Neither the name of the Chelsio Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <cxgb_include.h>
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/* Marvell PHY interrupt status bits. */
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#define MV_INTR_JABBER 0x0001
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#define MV_INTR_POLARITY_CHNG 0x0002
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#define MV_INTR_ENG_DETECT_CHNG 0x0010
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#define MV_INTR_DOWNSHIFT 0x0020
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#define MV_INTR_MDI_XOVER_CHNG 0x0040
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#define MV_INTR_FIFO_OVER_UNDER 0x0080
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#define MV_INTR_FALSE_CARRIER 0x0100
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#define MV_INTR_SYMBOL_ERROR 0x0200
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#define MV_INTR_LINK_CHNG 0x0400
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#define MV_INTR_AUTONEG_DONE 0x0800
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#define MV_INTR_PAGE_RECV 0x1000
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#define MV_INTR_DUPLEX_CHNG 0x2000
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#define MV_INTR_SPEED_CHNG 0x4000
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#define MV_INTR_AUTONEG_ERR 0x8000
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/* Marvell PHY specific registers. */
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#define MV88E1XXX_SPECIFIC_CNTRL 16
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#define MV88E1XXX_SPECIFIC_STATUS 17
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#define MV88E1XXX_INTR_ENABLE 18
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#define MV88E1XXX_INTR_STATUS 19
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#define MV88E1XXX_EXT_SPECIFIC_CNTRL 20
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#define MV88E1XXX_RECV_ERR 21
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#define MV88E1XXX_EXT_ADDR 22
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#define MV88E1XXX_GLOBAL_STATUS 23
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#define MV88E1XXX_LED_CNTRL 24
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#define MV88E1XXX_LED_OVERRIDE 25
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#define MV88E1XXX_EXT_SPECIFIC_CNTRL2 26
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#define MV88E1XXX_EXT_SPECIFIC_STATUS 27
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#define MV88E1XXX_VIRTUAL_CABLE_TESTER 28
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#define MV88E1XXX_EXTENDED_ADDR 29
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#define MV88E1XXX_EXTENDED_DATA 30
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/* PHY specific control register fields */
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#define S_PSCR_MDI_XOVER_MODE 5
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#define M_PSCR_MDI_XOVER_MODE 0x3
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#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
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/* Extended PHY specific control register fields */
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#define S_DOWNSHIFT_ENABLE 8
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#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
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#define S_DOWNSHIFT_CNT 9
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#define M_DOWNSHIFT_CNT 0x7
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#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
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/* PHY specific status register fields */
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#define S_PSSR_JABBER 0
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#define V_PSSR_JABBER (1 << S_PSSR_JABBER)
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#define S_PSSR_POLARITY 1
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#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
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#define S_PSSR_RX_PAUSE 2
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#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
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#define S_PSSR_TX_PAUSE 3
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#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
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#define S_PSSR_ENERGY_DETECT 4
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#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
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#define S_PSSR_DOWNSHIFT_STATUS 5
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#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
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#define S_PSSR_MDI 6
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#define V_PSSR_MDI (1 << S_PSSR_MDI)
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#define S_PSSR_CABLE_LEN 7
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#define M_PSSR_CABLE_LEN 0x7
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#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
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#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
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#define S_PSSR_LINK 10
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#define V_PSSR_LINK (1 << S_PSSR_LINK)
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#define S_PSSR_STATUS_RESOLVED 11
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#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
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#define S_PSSR_PAGE_RECEIVED 12
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#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
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#define S_PSSR_DUPLEX 13
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#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
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#define S_PSSR_SPEED 14
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#define M_PSSR_SPEED 0x3
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#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
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#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
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/* MV88E1XXX MDI crossover register values */
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#define CROSSOVER_MDI 0
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#define CROSSOVER_MDIX 1
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#define CROSSOVER_AUTO 3
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#define INTR_ENABLE_MASK (MV_INTR_SPEED_CHNG | MV_INTR_DUPLEX_CHNG | \
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MV_INTR_AUTONEG_DONE | MV_INTR_LINK_CHNG | MV_INTR_FIFO_OVER_UNDER | \
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MV_INTR_ENG_DETECT_CHNG)
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/*
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* Reset the PHY. If 'wait' is set wait until the reset completes.
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*/
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static int mv88e1xxx_reset(struct cphy *cphy, int wait)
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{
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return t3_phy_reset(cphy, 0, wait);
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}
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static int mv88e1xxx_intr_enable(struct cphy *cphy)
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{
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return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, INTR_ENABLE_MASK);
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}
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static int mv88e1xxx_intr_disable(struct cphy *cphy)
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{
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return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, 0);
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}
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static int mv88e1xxx_intr_clear(struct cphy *cphy)
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{
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u32 val;
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/* Clear PHY interrupts by reading the register. */
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return mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &val);
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}
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static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
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{
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return t3_mdio_change_bits(cphy, 0, MV88E1XXX_SPECIFIC_CNTRL,
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V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE),
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V_PSCR_MDI_XOVER_MODE(crossover));
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}
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static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
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{
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mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
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/* restart autoneg for change to take effect */
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return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
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BMCR_ANENABLE | BMCR_ANRESTART);
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}
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static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
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{
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return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
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BMCR_ANRESTART);
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}
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static int mv88e1xxx_set_loopback(struct cphy *cphy, int mmd, int dir, int on)
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{
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return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_LOOPBACK,
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on ? BMCR_LOOPBACK : 0);
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}
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static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_state,
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int *speed, int *duplex, int *fc)
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{
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u32 status;
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int sp = -1, dplx = -1, pause = 0;
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mdio_read(cphy, 0, MV88E1XXX_SPECIFIC_STATUS, &status);
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if ((status & V_PSSR_STATUS_RESOLVED) != 0) {
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if (status & V_PSSR_RX_PAUSE)
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pause |= PAUSE_RX;
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if (status & V_PSSR_TX_PAUSE)
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pause |= PAUSE_TX;
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dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
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sp = G_PSSR_SPEED(status);
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if (sp == 0)
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sp = SPEED_10;
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else if (sp == 1)
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sp = SPEED_100;
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else
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sp = SPEED_1000;
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}
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if (link_state)
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*link_state = status & V_PSSR_LINK ? PHY_LINK_UP :
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PHY_LINK_DOWN;
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if (speed)
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*speed = sp;
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if (duplex)
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*duplex = dplx;
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if (fc)
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*fc = pause;
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return 0;
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}
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static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex)
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{
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int err = t3_set_phy_speed_duplex(phy, speed, duplex);
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/* PHY needs reset for new settings to take effect */
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if (!err)
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err = mv88e1xxx_reset(phy, 0);
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return err;
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}
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static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
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{
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/*
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* Set the downshift counter to 2 so we try to establish Gb link
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* twice before downshifting.
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*/
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return t3_mdio_change_bits(cphy, 0, MV88E1XXX_EXT_SPECIFIC_CNTRL,
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V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT),
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downshift_enable ? V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2) : 0);
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}
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static int mv88e1xxx_power_down(struct cphy *cphy, int enable)
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{
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return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
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enable ? BMCR_PDOWN : 0);
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}
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static int mv88e1xxx_intr_handler(struct cphy *cphy)
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{
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const u32 link_change_intrs = MV_INTR_LINK_CHNG |
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MV_INTR_AUTONEG_DONE | MV_INTR_DUPLEX_CHNG |
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MV_INTR_SPEED_CHNG | MV_INTR_DOWNSHIFT;
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u32 cause;
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int cphy_cause = 0;
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mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &cause);
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cause &= INTR_ENABLE_MASK;
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if (cause & link_change_intrs)
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cphy_cause |= cphy_cause_link_change;
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if (cause & MV_INTR_FIFO_OVER_UNDER)
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cphy_cause |= cphy_cause_fifo_error;
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return cphy_cause;
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}
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#ifdef C99_NOT_SUPPORTED
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static struct cphy_ops mv88e1xxx_ops = {
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mv88e1xxx_reset,
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mv88e1xxx_intr_enable,
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mv88e1xxx_intr_disable,
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mv88e1xxx_intr_clear,
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mv88e1xxx_intr_handler,
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mv88e1xxx_autoneg_enable,
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mv88e1xxx_autoneg_restart,
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t3_phy_advertise,
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mv88e1xxx_set_loopback,
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mv88e1xxx_set_speed_duplex,
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mv88e1xxx_get_link_status,
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mv88e1xxx_power_down,
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};
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#else
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static struct cphy_ops mv88e1xxx_ops = {
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.reset = mv88e1xxx_reset,
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.intr_enable = mv88e1xxx_intr_enable,
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.intr_disable = mv88e1xxx_intr_disable,
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.intr_clear = mv88e1xxx_intr_clear,
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.intr_handler = mv88e1xxx_intr_handler,
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.autoneg_enable = mv88e1xxx_autoneg_enable,
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.autoneg_restart = mv88e1xxx_autoneg_restart,
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.advertise = t3_phy_advertise,
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.set_loopback = mv88e1xxx_set_loopback,
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.set_speed_duplex = mv88e1xxx_set_speed_duplex,
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.get_link_status = mv88e1xxx_get_link_status,
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.power_down = mv88e1xxx_power_down,
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};
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#endif
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int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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struct cphy *phy = &pinfo->phy;
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int err;
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cphy_init(phy, pinfo->adapter, pinfo, phy_addr, &mv88e1xxx_ops, mdio_ops,
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SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII |
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SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T");
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/* Configure copper PHY transmitter as class A to reduce EMI. */
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err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_ADDR, 0xb);
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if (!err)
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err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_DATA, 0x8004);
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if (!err)
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err = mv88e1xxx_downshift_set(phy, 1); /* Enable downshift */
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return err;
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}
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