cc9fce5ad7
HD64570 chip. Both the 2 and 4 port cards is supported and auto detected. Line speeds of up to 2Mbps is possible. At this speed about 85% of the bandwidth is usable with 486DX processors. The standard FreeBSD sppp code is used for the link level layer. The default protocol used is PPP. The Cisco HDLC protocol can be used by adding "link2" to the ifconfig line in /etc/sysconfig or where ever ifconfig is run. At the moment only the V.35 and X.21 interfaces is supported. The others may need tweaks to the clock selection code. Submitted by: John Hay <jhay@mikom.csir.co.za>
367 lines
12 KiB
C
367 lines
12 KiB
C
/*
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* Copyright (c) 1995 John Hay. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by [your name]
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* and [any other names deserving credit ]
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: hd64570.h,v 1.2 1995/11/08 16:20:35 jhay Exp $
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*/
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#ifndef _HD64570_H_
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#define _HD64570_H_
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typedef struct msci_channel
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{
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union
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{
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unsigned short us_trb; /* rw */
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struct
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{
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unsigned char uc_trbl;
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unsigned char uc_trbh;
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}uc_trb;
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}u_trb;
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unsigned char st0; /* ro */
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unsigned char st1; /* rw */
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unsigned char st2; /* rw */
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unsigned char st3; /* ro */
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unsigned char fst; /* rw */
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unsigned char unused0;
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unsigned char ie0; /* rw */
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unsigned char ie1; /* rw */
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unsigned char ie2; /* rw */
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unsigned char fie; /* rw */
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unsigned char cmd; /* wo */
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unsigned char unused1;
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unsigned char md0; /* rw */
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unsigned char md1; /* rw */
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unsigned char md2; /* rw */
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unsigned char ctl; /* rw */
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unsigned char sa0; /* rw */
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unsigned char sa1; /* rw */
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unsigned char idl; /* rw */
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unsigned char tmc; /* rw */
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unsigned char rxs; /* rw */
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unsigned char txs; /* rw */
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unsigned char trc0; /* rw */
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unsigned char trc1; /* rw */
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unsigned char rrc; /* rw */
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unsigned char unused2;
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unsigned char cst0; /* rw */
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unsigned char cst1; /* rw */
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unsigned char unused3[2];
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}msci_channel;
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#define trb u_trb.us_trb
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#define trbl u_trb.uc_trb.uc_trbl
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#define trbh u_trb.uc_trb.uc_trbh
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typedef struct timer_channel
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{
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unsigned short tcnt; /* rw */
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unsigned short tconr; /* wo */
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unsigned char tcsr; /* rw */
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unsigned char tepr; /* rw */
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unsigned char unused[2];
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}timer_channel;
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typedef struct dmac_channel
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{
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unsigned short dar; /* rw */
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unsigned char darb; /* rw */
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unsigned char unused0;
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unsigned short sar; /* rw On odd numbered dmacs (tx) only */
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unsigned char sarb; /* rw */
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#define cpb sarb;
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unsigned char unused1;
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unsigned short cda; /* rw */
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unsigned short eda; /* rw */
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unsigned short bfl; /* rw On even numbered dmacs (rx) only */
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unsigned short bcr; /* rw */
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unsigned char dsr; /* rw */
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unsigned char dmr; /* rw */
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unsigned char unused2;
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unsigned char fct; /* rw */
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unsigned char dir; /* rw */
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unsigned char dcr; /* rw */
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unsigned char unused3[10];
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}dmac_channel;
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/* x is the channel number. rx channels are even numbered and tx, odd. */
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#define DMAC_RXCH(x) ((x*2) + 0)
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#define DMAC_TXCH(x) ((x*2) + 1)
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typedef struct sca_regs
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{
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unsigned char lpr; /* rw */
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unsigned char unused0; /* -- */
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/* Wait system */
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unsigned char pabr0; /* rw */
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unsigned char pabr1; /* rw */
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unsigned char wcrl; /* rw */
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unsigned char wcrm; /* rw */
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unsigned char wcrh; /* rw */
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unsigned char unused1;
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/* DMAC */
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unsigned char pcr; /* rw */
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unsigned char dmer; /* rw */
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unsigned char unused2[6];
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/* Interrupt */
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unsigned char isr0; /* ro */
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unsigned char isr1; /* ro */
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unsigned char isr2; /* ro */
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unsigned char unused3;
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unsigned char ier0; /* rw */
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unsigned char ier1; /* rw */
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unsigned char ier2; /* rw */
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unsigned char unused4;
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unsigned char itcr; /* rw */
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unsigned char unused5;
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unsigned char ivr; /* rw */
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unsigned char unused6;
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unsigned char imvr; /* rw */
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unsigned char unused7[3];
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/* MSCI Channel 0 */
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msci_channel msci[2];
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timer_channel timer[4];
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dmac_channel dmac[4];
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}sca_regs;
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#define SCA_CMD_TXRESET 0x01
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#define SCA_CMD_TXENABLE 0x02
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#define SCA_CMD_TXDISABLE 0x03
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#define SCA_CMD_TXCRCINIT 0x04
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#define SCA_CMD_TXCRCEXCL 0x05
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#define SCA_CMS_TXEOM 0x06
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#define SCA_CMD_TXABORT 0x07
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#define SCA_CMD_MPON 0x08
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#define SCA_CMD_TXBCLEAR 0x09
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#define SCA_CMD_RXRESET 0x11
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#define SCA_CMD_RXENABLE 0x12
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#define SCA_CMD_RXDISABLE 0x13
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#define SCA_CMD_RXCRCINIT 0x14
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#define SCA_CMD_RXMSGREJ 0x15
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#define SCA_CMD_MPSEARCH 0x16
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#define SCA_CMD_RXCRCEXCL 0x17
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#define SCA_CMD_RXCRCCALC 0x18
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#define SCA_CMD_NOP 0x00
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#define SCA_CMD_RESET 0x21
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#define SCA_CMD_SEARCH 0x31
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#define SCA_MD0_CRC_1 0x01
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#define SCA_MD0_CRC_CCITT 0x02
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#define SCA_MD0_CRC_ENABLE 0x04
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#define SCA_MD0_AUTO_ENABLE 0x10
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#define SCA_MD0_MODE_ASYNC 0x00
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#define SCA_MD0_MODE_BYTESYNC1 0x20
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#define SCA_MD0_MODE_BISYNC 0x40
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#define SCA_MD0_MODE_BYTESYNC2 0x60
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#define SCA_MD0_MODE_HDLC 0x80
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#define SCA_MD1_NOADDRCHK 0x00
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#define SCA_MD1_SNGLADDR1 0x40
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#define SCA_MD1_SNGLADDR2 0x80
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#define SCA_MD1_DUALADDR 0xC0
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#define SCA_MD2_DUPLEX 0x00
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#define SCA_MD2_ECHO 0x01
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#define SCA_MD2_LOOPBACK 0x03
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#define SCA_MD2_ADPLLx8 0x00
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#define SCA_MD2_ADPLLx16 0x08
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#define SCA_MD2_ADPLLx32 0x10
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#define SCA_MD2_NRZ 0x00
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#define SCA_MD2_NRZI 0x20
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#define SCA_MD2_MANCHESTER 0x80
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#define SCA_MD2_FM0 0xC0
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#define SCA_MD2_FM1 0xA0
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#define SCA_CTL_RTS 0x01
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#define SCA_CTL_IDLPAT 0x10
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#define SCA_CTL_UDRNC 0x20
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#define SCA_RXS_DIV_MASK 0x0F
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#define SCA_RXS_DIV1 0x00
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#define SCA_RXS_DIV2 0x01
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#define SCA_RXS_DIV4 0x02
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#define SCA_RXS_DIV8 0x03
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#define SCA_RXS_DIV16 0x04
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#define SCA_RXS_DIV32 0x05
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#define SCA_RXS_DIV64 0x06
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#define SCA_RXS_DIV128 0x07
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#define SCA_RXS_DIV256 0x08
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#define SCA_RXS_DIV512 0x09
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#define SCA_RXS_CLK_RXC0 0x00
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#define SCA_RXS_CLK_RXC1 0x20
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#define SCA_RXS_CLK_INT 0x40
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#define SCA_RXS_CLK_ADPLL_OUT 0x60
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#define SCA_RXS_CLK_ADPLL_IN 0x70
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#define SCA_TXS_DIV_MASK 0x0F
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#define SCA_TXS_DIV1 0x00
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#define SCA_TXS_DIV2 0x01
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#define SCA_TXS_DIV4 0x02
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#define SCA_TXS_DIV8 0x03
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#define SCA_TXS_DIV16 0x04
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#define SCA_TXS_DIV32 0x05
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#define SCA_TXS_DIV64 0x06
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#define SCA_TXS_DIV128 0x07
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#define SCA_TXS_DIV256 0x08
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#define SCA_TXS_DIV512 0x09
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#define SCA_TXS_CLK_TXC 0x00
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#define SCA_TXS_CLK_INT 0x40
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#define SCA_TXS_CLK_RX 0x60
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#define SCA_ST0_RXRDY 0x01
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#define SCA_ST0_TXRDY 0x02
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#define SCA_ST0_RXINT 0x40
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#define SCA_ST0_TXINT 0x80
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#define SCA_ST1_IDLST 0x01
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#define SCA_ST1_ABTST 0x02
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#define SCA_ST1_DCDCHG 0x04
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#define SCA_ST1_CTSCHG 0x08
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#define SCA_ST1_FLAG 0x10
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#define SCA_ST1_TXIDL 0x40
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#define SCA_ST1_UDRN 0x80
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/* ST2 and FST look the same */
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#define SCA_FST_CRCERR 0x04
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#define SCA_FST_OVRN 0x08
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#define SCA_FST_RESFRM 0x10
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#define SCA_FST_ABRT 0x20
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#define SCA_FST_SHRT 0x40
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#define SCA_FST_EOM 0x80
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#define SCA_ST3_RXENA 0x01
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#define SCA_ST3_TXENA 0x02
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#define SCA_ST3_DCD 0x04
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#define SCA_ST3_CTS 0x08
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#define SCA_ST3_ADPLLSRCH 0x10
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#define SCA_ST3_TXDATA 0x20
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#define SCA_FIE_EOMFE 0x80
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#define SCA_IE0_RXRDY 0x01
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#define SCA_IE0_TXRDY 0x02
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#define SCA_IE0_RXINT 0x40
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#define SCA_IE0_TXINT 0x80
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#define SCA_IE1_IDLDE 0x01
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#define SCA_IE1_ABTDE 0x02
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#define SCA_IE1_DCD 0x04
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#define SCA_IE1_CTS 0x08
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#define SCA_IE1_FLAG 0x10
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#define SCA_IE1_IDL 0x40
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#define SCA_IE1_UDRN 0x80
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#define SCA_IE2_CRCERR 0x04
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#define SCA_IE2_OVRN 0x08
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#define SCA_IE2_RESFRM 0x10
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#define SCA_IE2_ABRT 0x20
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#define SCA_IE2_SHRT 0x40
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#define SCA_IE2_EOM 0x80
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/* This is for RRC, TRC0 and TRC1. */
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#define SCA_RCR_MASK 0x1F
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#define SCA_IE1_
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#define SCA_IV_CHAN0 0x00
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#define SCA_IV_CHAN1 0x20
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#define SCA_IV_RXRDY 0x04
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#define SCA_IV_TXRDY 0x06
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#define SCA_IV_RXINT 0x08
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#define SCA_IV_TXINT 0x0A
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#define SCA_IV_DMACH0 0x00
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#define SCA_IV_DMACH1 0x08
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#define SCA_IV_DMACH2 0x20
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#define SCA_IV_DMACH3 0x28
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#define SCA_IV_DMIA 0x14
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#define SCA_IV_DMIB 0x16
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#define SCA_IV_TIMER0 0x1C
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#define SCA_IV_TIMER1 0x1E
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#define SCA_IV_TIMER2 0x3C
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#define SCA_IV_TIMER3 0x3E
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/*
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* DMA registers
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*/
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#define SCA_DSR_EOT 0x80
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#define SCA_DSR_EOM 0x40
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#define SCA_DSR_BOF 0x20
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#define SCA_DSR_COF 0x10
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#define SCA_DSR_DE 0x02
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#define SCA_DSR_DWE 0x01
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#define SCA_DMR_TMOD 0x10
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#define SCA_DMR_NF 0x04
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#define SCA_DMR_CNTE 0x02
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#define SCA_DMER_EN 0x80
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#define SCA_DCR_ABRT 0x01
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#define SCA_DCR_FCCLR 0x02 /* Clear frame end intr counter */
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#define SCA_DIR_EOT 0x80
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#define SCA_DIR_EOM 0x40
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#define SCA_DIR_BOF 0x20
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#define SCA_DIR_COF 0x10
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typedef struct sca_descriptor
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{
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unsigned short cp;
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unsigned short bp;
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unsigned char bpb;
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unsigned char unused0;
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unsigned short len;
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unsigned char stat;
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unsigned char unused1;
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}sca_descriptor;
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#define SCA_DESC_EOT 0x01
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#define SCA_DESC_CRC 0x04
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#define SCA_DESC_OVRN 0x08
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#define SCA_DESC_RESD 0x10
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#define SCA_DESC_ABORT 0x20
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#define SCA_DESC_SHRTFRM 0x40
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#define SCA_DESC_EOM 0x80
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#define SCA_DESC_ERRORS 0x7C
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/*
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***************************************************************************
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** END
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***************************************************************************
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**/
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#endif /* _HD64570_H_ */
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