155781198a
drivers, there should be a 1us delay after every write when bit-banging the MII. Also insert barriers in order to ensure the intended ordering. These changes hopefully will solve the bus wedging occasionally experienced with DM9102A since r182461. - Deobfuscate dc_mii_readreg() a bit. |
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dcphy.c | ||
if_dc.c | ||
if_dcreg.h | ||
pnphy.c |