088dd4b78a
requires 8 bytes alignment on RX buffer. Given that non-jumbo frame works on any alignments I guess this DMA limitation for RX buffer could be jumbo frame specific one. Also I'm not sure whether this DMA limitation is related with 64bit DMA. Previously age(4) disabled 64bit DMA addressing due to silent data corruption. So we may need more testing on re-enabling 64bit DMA in future. While I'm here, change mbuf chaining algorithm to use fixed sized buffer and force software checksum if controller reports length error. According to QAC, RFD is not updated at all for jumbo frame so it works just like alc(4) controllers. This change also added alignment fixup for strict alignment architectures. Because I'm not aware of any non-x86 machines that use age(4) controllers it's just for completeness at this moment. Wit this change, jumbo frame should work with age(4). Tested by: Christian Gusenbauer < c47g <> gmx dot at > MFC after: 1 week
276 lines
7.8 KiB
C
276 lines
7.8 KiB
C
/*-
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* Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_AGEVAR_H
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#define _IF_AGEVAR_H
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#define AGE_TX_RING_CNT 256
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#define AGE_RX_RING_CNT 256
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#define AGE_RR_RING_CNT (AGE_TX_RING_CNT + AGE_RX_RING_CNT)
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/* The following ring alignments are just guessing. */
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#define AGE_TX_RING_ALIGN 16
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#define AGE_RX_RING_ALIGN 16
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#define AGE_RR_RING_ALIGN 16
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#define AGE_CMB_ALIGN 16
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#define AGE_SMB_ALIGN 16
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#define AGE_TSO_MAXSEGSIZE 4096
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#define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
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#define AGE_MAXTXSEGS 32
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#define AGE_RX_BUF_ALIGN 8
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#ifndef __NO_STRICT_ALIGNMENT
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#define AGE_RX_BUF_SIZE (MCLBYTES - AGE_RX_BUF_ALIGN)
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#else
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#define AGE_RX_BUF_SIZE (MCLBYTES)
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#endif
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#define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
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#define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32)
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#define AGE_MSI_MESSAGES 1
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#define AGE_MSIX_MESSAGES 1
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/* TODO : Should get real jumbo MTU size. */
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#define AGE_JUMBO_FRAMELEN 10240
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#define AGE_JUMBO_MTU \
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(AGE_JUMBO_FRAMELEN - ETHER_VLAN_ENCAP_LEN - \
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ETHER_HDR_LEN - ETHER_CRC_LEN)
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#define AGE_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
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#define AGE_PROC_MIN 30
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#define AGE_PROC_MAX (AGE_RX_RING_CNT - 1)
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#define AGE_PROC_DEFAULT (AGE_RX_RING_CNT / 2)
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struct age_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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struct tx_desc *tx_desc;
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};
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struct age_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct rx_desc *rx_desc;
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};
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struct age_chain_data{
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bus_dma_tag_t age_parent_tag;
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bus_dma_tag_t age_buffer_tag;
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bus_dma_tag_t age_tx_tag;
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struct age_txdesc age_txdesc[AGE_TX_RING_CNT];
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bus_dma_tag_t age_rx_tag;
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struct age_rxdesc age_rxdesc[AGE_RX_RING_CNT];
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bus_dma_tag_t age_tx_ring_tag;
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bus_dmamap_t age_tx_ring_map;
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bus_dma_tag_t age_rx_ring_tag;
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bus_dmamap_t age_rx_ring_map;
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bus_dmamap_t age_rx_sparemap;
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bus_dma_tag_t age_rr_ring_tag;
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bus_dmamap_t age_rr_ring_map;
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bus_dma_tag_t age_cmb_block_tag;
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bus_dmamap_t age_cmb_block_map;
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bus_dma_tag_t age_smb_block_tag;
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bus_dmamap_t age_smb_block_map;
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int age_tx_prod;
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int age_tx_cons;
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int age_tx_cnt;
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int age_rx_cons;
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int age_rr_cons;
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int age_rxlen;
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struct mbuf *age_rxhead;
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struct mbuf *age_rxtail;
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struct mbuf *age_rxprev_tail;
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};
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struct age_ring_data {
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struct tx_desc *age_tx_ring;
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bus_addr_t age_tx_ring_paddr;
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struct rx_desc *age_rx_ring;
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bus_addr_t age_rx_ring_paddr;
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struct rx_rdesc *age_rr_ring;
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bus_addr_t age_rr_ring_paddr;
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struct cmb *age_cmb_block;
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bus_addr_t age_cmb_block_paddr;
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struct smb *age_smb_block;
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bus_addr_t age_smb_block_paddr;
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};
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#define AGE_TX_RING_SZ \
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(sizeof(struct tx_desc) * AGE_TX_RING_CNT)
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#define AGE_RX_RING_SZ \
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(sizeof(struct rx_desc) * AGE_RX_RING_CNT)
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#define AGE_RR_RING_SZ \
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(sizeof(struct rx_rdesc) * AGE_RR_RING_CNT)
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#define AGE_CMB_BLOCK_SZ sizeof(struct cmb)
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#define AGE_SMB_BLOCK_SZ sizeof(struct smb)
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struct age_stats {
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/* Rx stats. */
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uint64_t rx_frames;
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uint64_t rx_bcast_frames;
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uint64_t rx_mcast_frames;
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uint32_t rx_pause_frames;
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uint32_t rx_control_frames;
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uint32_t rx_crcerrs;
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uint32_t rx_lenerrs;
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uint64_t rx_bytes;
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uint32_t rx_runts;
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uint64_t rx_fragments;
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uint64_t rx_pkts_64;
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uint64_t rx_pkts_65_127;
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uint64_t rx_pkts_128_255;
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uint64_t rx_pkts_256_511;
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uint64_t rx_pkts_512_1023;
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uint64_t rx_pkts_1024_1518;
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uint64_t rx_pkts_1519_max;
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uint64_t rx_pkts_truncated;
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uint32_t rx_fifo_oflows;
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uint32_t rx_desc_oflows;
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uint32_t rx_alignerrs;
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uint64_t rx_bcast_bytes;
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uint64_t rx_mcast_bytes;
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uint64_t rx_pkts_filtered;
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/* Tx stats. */
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uint64_t tx_frames;
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uint64_t tx_bcast_frames;
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uint64_t tx_mcast_frames;
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uint32_t tx_pause_frames;
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uint32_t tx_excess_defer;
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uint32_t tx_control_frames;
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uint32_t tx_deferred;
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uint64_t tx_bytes;
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uint64_t tx_pkts_64;
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uint64_t tx_pkts_65_127;
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uint64_t tx_pkts_128_255;
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uint64_t tx_pkts_256_511;
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uint64_t tx_pkts_512_1023;
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uint64_t tx_pkts_1024_1518;
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uint64_t tx_pkts_1519_max;
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uint32_t tx_single_colls;
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uint32_t tx_multi_colls;
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uint32_t tx_late_colls;
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uint32_t tx_excess_colls;
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uint32_t tx_underrun;
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uint32_t tx_desc_underrun;
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uint32_t tx_lenerrs;
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uint32_t tx_pkts_truncated;
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uint64_t tx_bcast_bytes;
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uint64_t tx_mcast_bytes;
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};
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/*
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* Software state per device.
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*/
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struct age_softc {
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struct ifnet *age_ifp;
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device_t age_dev;
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device_t age_miibus;
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struct resource *age_res[1];
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struct resource_spec *age_res_spec;
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struct resource *age_irq[AGE_MSI_MESSAGES];
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struct resource_spec *age_irq_spec;
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void *age_intrhand[AGE_MSI_MESSAGES];
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int age_rev;
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int age_chip_rev;
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int age_phyaddr;
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uint8_t age_eaddr[ETHER_ADDR_LEN];
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uint32_t age_dma_rd_burst;
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uint32_t age_dma_wr_burst;
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int age_flags;
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#define AGE_FLAG_PCIE 0x0001
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#define AGE_FLAG_PCIX 0x0002
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#define AGE_FLAG_MSI 0x0004
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#define AGE_FLAG_MSIX 0x0008
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#define AGE_FLAG_PMCAP 0x0010
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#define AGE_FLAG_DETACH 0x4000
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#define AGE_FLAG_LINK 0x8000
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struct callout age_tick_ch;
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struct age_stats age_stat;
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struct age_chain_data age_cdata;
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struct age_ring_data age_rdata;
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int age_if_flags;
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int age_watchdog_timer;
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int age_process_limit;
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int age_int_mod;
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int age_max_frame_size;
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int age_morework;
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int age_rr_prod;
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int age_tpd_cons;
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struct task age_int_task;
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struct task age_link_task;
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struct taskqueue *age_tq;
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struct mtx age_mtx;
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};
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/* Register access macros. */
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#define CSR_WRITE_4(_sc, reg, val) \
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bus_write_4((_sc)->age_res[0], (reg), (val))
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#define CSR_WRITE_2(_sc, reg, val) \
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bus_write_2((_sc)->age_res[0], (reg), (val))
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#define CSR_READ_2(_sc, reg) \
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bus_read_2((_sc)->age_res[0], (reg))
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#define CSR_READ_4(_sc, reg) \
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bus_read_4((_sc)->age_res[0], (reg))
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#define AGE_LOCK(_sc) mtx_lock(&(_sc)->age_mtx)
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#define AGE_UNLOCK(_sc) mtx_unlock(&(_sc)->age_mtx)
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#define AGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->age_mtx, MA_OWNED)
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#define AGE_COMMIT_MBOX(_sc) \
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do { \
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CSR_WRITE_4(_sc, AGE_MBOX, \
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(((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \
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MBOX_RD_PROD_IDX_MASK) | \
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(((_sc)->age_cdata.age_rr_cons << \
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MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) | \
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(((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \
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MBOX_TD_PROD_IDX_MASK)); \
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} while (0)
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#define AGE_RXCHAIN_RESET(_sc) \
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do { \
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(_sc)->age_cdata.age_rxhead = NULL; \
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(_sc)->age_cdata.age_rxtail = NULL; \
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(_sc)->age_cdata.age_rxprev_tail = NULL; \
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(_sc)->age_cdata.age_rxlen = 0; \
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} while (0)
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#define AGE_TX_TIMEOUT 5
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#define AGE_RESET_TIMEOUT 100
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#define AGE_TIMEOUT 1000
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#define AGE_PHY_TIMEOUT 1000
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#endif /* _IF_AGEVAR_H */
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